TPA6203A1DRBRG4 datasheet(8/27 Pages) TI

部件名	TPA6203A1DRBRG4

功能描述	1.25-W MONO FULLY DIFFERENTIAL AUDIO POWER AMPLIFIER

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制造商	TI [Texas Instruments]

网页	http://www.ti.com

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f - Frequency - Hz

0

-50

-100

0

200 400 600 800 1k 1.2k 1.4k 1.6k 1.8k 2k

-150

-100

0

-50

VDD Shown in Figure 19

CI = 2 µF,

C(Bypass) = 0.47 µF,

Inputs ac-Grounded

Gain = 1V/V

C1

Frequency

217.41 Hz

C1 - Duty

20 %

C1 High

3.598 V

C1 Pk-Pk

504 mV

Ch1 100 mV/div

Ch4 10 mV/div

2 ms/div

t - Time - ms

VDD

VO

-100

0

-90

-80

-70

-60

-50

-40

-30

-20

-10

20

20 k

50 100 200

500 1 k 2 k

5 k 10 k

f - Frequency - Hz

VDD = 2.5 V to 5 V

VIC = 200 mVp-p

RL = 8 Ω

Gain = 1 V/V

-70

-60

-50

-40

-30

-20

-10

0

10

20

30

40

10

100

10 k

100 k 1 M

10 M

-220

-180

-140

-100

-60

-20

20

60

100

140

180

220

1 k

f - Frequency - Hz

Gain

Phase

VDD = 3.6 V

RL = 8 Ω

Gain = 1 V/V

-200

-150

-100

-50

0

50

100

150

200

100

1 k

10 k

100 k

1 M

-200

-150

-100

-50

0

50

100

150

200

f - Frequency - Hz

Gain

Phase

VDD = 3.6 V

RL = 8 Ω

10 M

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

0.5 1

1.5 2

2.5 3

3.5 4

4.5 5

RL = 8 Ω

Gain = 1 V/V

VIC - Common Mode Input Voltage - V

VDD = 3.6 V

VDD = 5 V

VDD = 2.5 V

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

0 0.5 1

1.5 2 2.5

3 3.5

4 4.5 5

5.5

VDD - Supply Voltage - V

0

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

1

1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9

2

VDD = 2.5 V

VDD = 3.6 V

VDD = 5 V

Voltage on SHUTDOWN Terminal - V

0.2

0

1

2

3

4

5

6

0

0.5

1

1.5

2

C(Bypass) - Bypass Capacitor - µF

(1) Start-Up time is the time it takes (from a

low-to-high transition on SHUTDOWN) for the

gain of the amplifier to reach -3 dB of the final

gain.

TPA6203A1

SLOS364E – MARCH 2002 – REVISED DECEMBER 2005

TYPICAL CHARACTERISTICS (continued)

GSM POWER SUPPLY

COMMON MODE REJECTION RATIO

REJECTION

vs

FREQUENCY

TIME

FREQUENCY

Figure 19.

Figure 20.

Figure 21.

COMMON MODE REJECTION RATIO

CLOSED LOOP GAIN/PHASE

OPEN LOOP GAIN/PHASE

vs

COMMON MODE INPUT VOLTAGE

FREQUENCY

Figure 22.

Figure 23.

Figure 24.

SUPPLY CURRENT

START-UP TIME(1)

vs

SUPPLY VOLTAGE

SHUTDOWN VOLTAGE

BYPASS CAPACITOR

Figure 25.

Figure 26.

Figure 27.

8

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