MC145202

MOTOROLA

5

AC INTERFACE CHARACTERISTICS

(VDD = VCC = 2.7 to 5.5 V, TA = – 40 to + 85°C, CL = 25 pF, Input tr = tf = 10 ns; VPD = 2.7 to 5.5 V)

Symbol

Parameter

Figure

No.

Guaranteed

Limit

Unit

fclk

Serial Data Clock Frequency (Note: Refer to Clock tw below)

1

dc to 4.0

MHz

tPLH, tPHL Maximum Propagation Delay, CLK to OUTPUT A (Selected as Data Out)

1, 5

100

ns

tPLH, tPHL Maximum Propagation Delay, ENB to OUTPUT A (Selected as Port)

2, 5

150

ns

tPZL, tPLZ

Maximum Propagation Delay, ENB to OUTPUT B

2, 6

150

ns

tTLH, tTHL

Maximum Output Transition Time, OUTPUT A and OUTPUT B; tTHLonly, on OUTPUT B

1, 5, 6

50

ns

Cin

Maximum Input Capacitance – Din, ENB, CLK

10

pF

TIMING REQUIREMENTS

(VDD = VCC = 2.7 to 5.5 V, TA = – 40 to + 85°C, Input tr = tf = 10 ns, unless otherwise indicated)

Symbol

Parameter

Figure

No.

Guaranteed

Limit

Unit

tsu, th

Minimum Setup and Hold Times, Din vs CLK

3

50

ns

tsu, th, trec

Minimum Setup, Hold and Recovery Times, ENB vs CLK

4

100

ns

tw

Minimum Pulse Width, ENB

4

*

cycles

tw

Minimum Pulse Width, CLK

1

125

ns

tr, tf

Maximum Input Rise and Fall Times, CLK

1

100

µs

* The minimum limit is 3 REFin cycles or 195 fin cycles, whichever is greater.