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CD74AC109M96E4 数据表(PDF) 7 Page - Texas Instruments |
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CD74AC109M96E4 数据表(HTML) 7 Page - Texas Instruments |
7 / 12 page CD54AC109, CD74AC109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS326 – JANUARY 2003 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES th tsu 50% VCC 50% VCC 50% 10% 10% 90% 90% VCC VCC 0 V 0 V tr tf Reference Input Data Input VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES 50% VCC 50% VCC 50% 10% 10% 90% 90% VCC VOH VOL 0 V tr tf Input In-Phase Output 50% VCC tPLH tPHL 50% VCC 50% 10% 10% 90% 90% VOH VOL tr tf tPHL tPLH Out-of-Phase Output NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. Phase relationships between waveforms are arbitrary. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLH and tPHL are the same as tpd. G. tPZL and tPZH are the same as ten. H. tPLZ and tPHZ are the same as tdis. I. All parameters and waveforms are not applicable to all devices. From Output Under Test CL = 50 pF (see Note A) LOAD CIRCUIT S1 2 × VCC R1 = 500 Ω† Open GND 0 V tw VOLTAGE WAVEFORMS PULSE DURATION Input 50% VCC 50% VCC VCC tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND TEST S1 Output Control Output Waveform 1 S1 at 2 × VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) VOL VOH tPZL tPZH tPLZ tPHZ ≈VCC 0 V 50% VCC 20% VCC 50% VCC ≈0 V VOLTAGE WAVEFORMS OUTPUT ENABLE AND DISABLE TIMES 50% VCC 50% VCC 80% VCC VCC R2 = 500 Ω† † When VCC = 1.5 V, R1 = R2 = 1 kΩ VOLTAGE WAVEFORMS RECOVERY TIME 50% VCC VCC 0 V CLR Input CLK 50% VCC VCC trec 0 V Figure 1. Load Circuit and Voltage Waveforms |
类似零件编号 - CD74AC109M96E4 |
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类似说明 - CD74AC109M96E4 |
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