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UC2855ADW 数据表(PDF) 5 Page - Texas Instruments |
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UC2855ADW 数据表(HTML) 5 Page - Texas Instruments |
5 / 12 page 5 UC2855A/B UC3855A/B GTOUT: The output of the PWM is a 1.5A peak totem pole MOSFET gate driver on GTOUT. A series resistor between GTOUT and the MOSFET gate of at least 10 ohms should be used to limit the overshoot on GTOUT. In addition, a low VF Schottky diode should be connected between GTOUT and GND to limit undershoot and possi- ble erratic operation. IAC: This is a current input to the multiplier. The current into this pin should correspond to the instantaneous value of the rectified AC input line voltage. This is ac- complished by connecting a resistor directly between IAC and the rectified input line voltage. The nominal 650mV level present on IAC negates the need for any additional compensating resistors to accommodate for the zero crossings of the line. A current equal to one fourth of the IAC current forms one of the inductor current synthesizer inputs. IMO: This is the output of the multiplier, and the non- inverting input of the current amplifier. Since this output is a current, connect a resistor between this pin and ground equal in value to the input resistor of the current amplifier. The common mode operating range for this pin is −0.3V to 5V. ION: This pin is the current sensing input. It should be connected to the secondary side output of a current sensing transformer whose primary winding is in series with the boost switch. The resultant signal applied to this input is buffered and level shifted up a diode to the CI ca- pacitor on the CI pin. The ION buffer has a source only output. Discharge of the CI cap is enabled through the current synthesizer circuitry. The current sense trans- former termination resistor should be designed to obtain a 1V input signal amplitude at peak switch current. OVP: This pin senses the boost output voltage through a voltage divider. The enable comparator input is TTL com- patible and can be used as a remote shutdown port. A voltage level below 1.8V, disables VREF, oscillator, and the PWM circuitry via the enable comparator. Between 1.8V and VREF (7.5V) the UC is enabled. Voltage levels above 7.5V will set the PWM latch via the hysteretic OVP comparator and disable both ZVTOUT and GTOUT until the OVP level has decayed by the nominal hysteresis of 400mV. If the voltage divider is designed to initiate an OVP fault at 5% of OV, the internal hysteresis enables normal operation again when the output voltage has reached its nominal regulation level. Both the OVP and enable comparators have direct logical connections to the PWM output and exhibit typical propagation delays of 200ns. REF: REF is the output of the precision reference. The output is capable of supplying 25mA to peripheral cir- cuitry and is internally short circuit current limited. REF is disabled and low whenever VCC is below the UVLO threshold, and when OVP is below 1.8V. A REF “GOOD” comparator senses REF and disables the stage until REF has attained approximately 90% of its nominal value. Bypass REF to GND with a 0.1 µF or larger ce- ramic capacitor for best stability. RVS: The nominal 3V signal present on the VSENSE pin is buffered and brought out to the RVS pin. A current pro- portional to the output voltage is generated by connect- ing a resistor between this pin and GND. This current forms the second input to the current synthesizer. VAO: This is the output of the voltage amplifier. At a given input RMS voltage, the voltage on this pin will vary directly with the output load. The output swing is limited from approximately 100mV to 6V. Voltage levels below 1.5V on this pin will inhibit the multiplier output. VCC: Positive supply rail for the IC. Bypass this pin to GND with a 1 µF low ESL, ESR ceramic capacitor. This pin is internally clamped to 20V. Current into this clamp should be limited to less than 10mA. The UC3855A has a 15.5V (nominal) turn on threshold with 6 volts of hys- teresis while the UC3855B turns on at 10.5V with 500mV of hysteresis. VRMS: This pin is the feedforward line voltage compen- sation input to the multiplier. A voltage on VRMS propor- tional to the AC input RMS voltage commands the multiplier to alter the current command signal by 1/VRMS 2 to maintain a constant power balance. The in- put to VRMS is generally derived from a two pole low pass filter/voltage divider connected to the rectified AC input voltage. This feature allows universal input supply voltage operation and faster response to input line fluc- tuations for the PFC boost preregulator. For most de- signs, a voltage level of 1.5V on this pin should correspond to low line, and 4.7V for high line. The input range for this pin extends from 0 to 5.5V. VSENSE: This pin is the inverting input of the voltage amplifier and serves as the output voltage feedback point for the PFC boost converter. It senses the output voltage through a voltage divider which produces a nominal 3V. The voltage loop compensation is normally connected between this pin and VAO. The VSENSE pin must be above 1.5V at 25°C, (1.9V at –55°C) for the current syn- thesizer to work properly. PIN DESCRIPTIONS (cont.) |
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类似说明 - UC2855ADW |
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