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MC100EL34D 数据表(PDF) 5 Page - ON Semiconductor |
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MC100EL34D 数据表(HTML) 5 Page - ON Semiconductor |
5 / 8 page MC10EL34, MC100EL34 http://onsemi.com 5 AC CHARACTERISTICS VCC= 5.0 V; VEE= 0.0 V or VCC= 0.0 V; VEE= –5.0 V (Note 1.) –40 °C 25 °C 85 °C Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit fmax Maximum Toggle Frequency TBD TBD TBD GHz tPLH tPHL Propagation CLK to Q0 Delay to CLK to Q1,2 Output MR to Q 960 900 750 1200 1140 1060 960 900 750 1200 1140 1060 970 910 790 1210 1150 1090 ps tSKEW Within-Device Skew (Note 2.) 100 100 100 ps tJITTER Cycle–to–Cycle Jitter TBD TBD TBD ps tS Setup Time EN 400 400 400 ps tH Hold Time EN 250 250 250 ps tRR Set/Reset Recovery 400 200 400 200 400 200 ps VPP Input Swing (Note 3.) 150 1000 150 1000 150 1000 mV tr tf Output Rise/Fall Times Q (20% – 80%) 275 525 275 525 275 525 ps 1. 10 Series: VEE can vary +0.06 V / –0.5 V. 100 Series: VEE can vary +0.8 V / –0.5 V. 2. Within-device skew is defined as identical transitions on similar paths through a device. 3. VPP(min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈40. Figure 1. Timing Diagram CLK Q0 Q1 Q2 EN The EN signal will freeze the internal clocks to the flip–flops on the first falling edge of CLK after its assertion. The internal dividers will maintain their state during the internal clock freeze and will return to clocking once the internal clocks are unfrozen. The outputs will transition to their next states in the same manner, time and relationship as they would have had the EN signal not been asserted. Internal Clock Disabled Internal Clock Enabled RESET tRR |
类似零件编号 - MC100EL34D |
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类似说明 - MC100EL34D |
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