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SN74GTLP2034DGVR 数据表(PDF) 3 Page - Texas Instruments

部件名 SN74GTLP2034DGVR
功能描述  8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

SN74GTLP2034DGVR 数据表(HTML) 3 Page - Texas Instruments

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SN74GTLP2034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
TSSOP – DGG
Tape and reel
SN74GTLP2034DGGR
GTLP2034
–40
°C to 85°C
TVSOP – DGV
Tape and reel
SN74GTLP2034DGVR
GT2034
VFBGA – GQL
Tape and reel
SN74GTLP2034GQLR
GR034
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
functional description
The SN74GTLP2034 is a high-drive (100 mA), 8-bit, three-wire registered transceiver containing D-type latches
and D-type flip-flops for data-path operation in the transparent, latched, or flip-flop modes. Data transmission
is true, with AI data going to the B port and B data going to AO. The split LVTTL AI and AO provides a feedback
path for control and diagnostics monitoring.
The logic element for data flow in each direction is configured by two mode (IMODE1 and IMODE0 for B to A,
OMODE1 and OMODE0 for A to B) inputs as a buffer, D-type flip-flop, or D-type latch. When configured in the
buffer mode, the input data appears at the output port. In the flip-flop mode, data is stored on the rising edge
of the appropriate clock (CLKAB/LEAB or CLKBA/LEBA) input. In the latch mode, the clock inputs serve as
active-high transparent latch enables.
Data flow in the B-to-A direction, regardless of the logic element selected, is further controlled by the
LOOPBACK input. When LOOPBACK is low, B-port data is the B-to-A input. When LOOPBACK is high, the
output of the selected A-to-B logic element is the B-to-A input.
The AO enable/disable control is provided by OEBA. When OEBA is low or when VCC is less than 1.5 V, AO
is in the high-impedance state. When OEBA is high, AO is active (high or low logic levels).
The B port is controlled by OEAB and OEAB. If OEAB is low, OEAB is high, or VCC is less than 1.5 V, the B port
is inactive. If OEAB is high and OEAB is low, the B port is active.
The A-to-B and B-to-A logic elements are active, regardless of the state of their associated outputs. The logic
elements can enter new data (in flip-flop and latch modes) or retain previously stored data while the associated
outputs are in the high-impedance (AO) or inactive (B port) states.


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