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AD7641BCPZRL 数据表(PDF) 7 Page - Analog Devices

部件名 AD7641BCPZRL
功能描述  18-Bit 250/670 kSPS PulSAR Bipolar Programmable Inputs ADC
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD7641BCPZRL 数据表(HTML) 7 Page - Analog Devices

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Preliminary Technical Data
AD7631/AD7634
Rev. PrC | Page 7 of 14
Parameter
Symbol
Min
Typ
Max
Unit
BUSY High in Master Serial Read after Convert4
t28
See
Table 4
CNVST Low to SYNC Asserted Delay (all Modes)
t29
ns
AD7631
TBD
ns
AD7634 (Warp Mode/Normal Mode/Impulse Mode)
TBD
ns
SYNC Deasserted to BUSY Low Delay
t30
25
ns
SLAVE SERIAL INTERFACE MODES
External SCLK Setup Time
t31
5
ns
External SCLK Active Edge to SDOUT Delay
t32
1
8
ns
SDIN Setup Time
t33
5
ns
SDIN Hold Time
t34
5
ns
External SCLK Period
t35
12.5
ns
External SCLK High
t36
5
ns
External SCLK Low
t37
5
ns
1 In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
2 In warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time.
3 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
4 In serial master read during convert mode. See Error! Reference source not found. for serial master read after convert mode timing specifications.
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1]
0
0
1
1
DIVSCLK[0]
Symbol
0
1
0
1
Unit
SYNC to SCLK First Edge Delay Minimum
t18
3
17
17
17
ns
Internal SCLK Period Minimum
t19
25
60
120
240
ns
Internal SCLK Period Maximum
t19
40
80
160
320
ns
Internal SCLK High Minimum
t20
12
22
50
100
ns
Internal SCLK Low Minimum
t21
7
21
49
99
ns
SDOUT Valid Setup Time Minimum
t22
4
18
18
18
ns
SDOUT Valid Hold Time Minimum
t23
2
4
30
89
ns
SCLK Last Edge to SYNC Delay Minimum
t24
3
60
140
300
ns
BUSY High Width Maximum (Warp mode)
t28
1.75
2.5
4
7
μs
BUSY High Width Maximum (Normal mode)
t28
2
2.75
4.25
7.25
μs
BUSY High Width Maximum (Impulse mode)
t28
2.25
3
4.5
7.5
μs


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