AD1970JSTZ datasheet(5/20 Pages) AD

部件名	AD1970JSTZ

功能描述	Digital BTSC Encoder with Integrated ADC and DAC

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制造商	AD [Analog Devices]

网页	http://www.analog.com

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5 / 20 page

AD1970

Rev. 0 | Page 5 of 20

Table 10. Digital Timing

Parameter

Min

Typ

Max

Unit

tDMD

MCLK Duty Cycle, External 512 fS Mode

40

50

60

%

tDBL

MCLK Low Pulse Width, External 512 fS Mode

15

ns

tDBH

MCLK High Pulse Width, External 512 fS Mode

15

ns

tDBL

MCLK Low Pulse Width, PLL, 256 fS or fS Mode

15

ns

tDBH

MCLK High Pulse Width, PLL, 256 fS or fS Mode

15

ns

tDLS

LRCLK Setup

10

ns

tDLH

LRCLK Hold

10

ns

tDDS

SDATA Setup

10

ns

tDDH

SDATA Hold

10

ns

tIBC

I2C Bus Clock Frequency

400

kHz

tISST

I2C Setup Time for Start Condition

10

ns

tIH

I2C Hold Time for Start Condition

30

ns

tSDS

SDA Setup Time

50

ns

tSDH

SDA Hold Time

25

ns

tSDF

SDA Fall Time at 3 mA Sink and 400 pF Load

25

ns

tSDR

SDA Rise Time

300

ns

tPWS

Pulse Width of Spikes Supressed by the Input Filter

50

ns

tPDRP

RESETB Low Pulse Width

15

ns

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