Preliminary Data Sheet

AD8196

PrA | Page 3 of 24

SPECIFICATIONS

1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.

Table 1.

Parameter

Conditions/Comments

Min

Typ

Max

Unit

DYNAMIC PERFORMANCE

Maximum Data Rate (DR) per Channel

NRZ

2.25

Gbps

Bit Error Rate (BER)

Added Deterministic Jitter

DR

TBD

ps (p-p)

Added Random Jitter

TBD

ps (rms)

Differential Intrapair Skew

At output

TBD

ps

Differential Interpair Skew1

At output

TBD

ps

EQUALIZATION PERFORMANCE

Receiver (Highest Setting)2

Boost frequency = 825 MHz

12

dB

Transmitter (Highest Setting)3

Boost frequency = 825 MHz

6

dB

INPUT CHARACTERISTICS

Input Voltage Swing

Differential

150

1200

mV

AVCC − 800

AVCC

mV

OUTPUT CHARACTERISTICS

High Voltage Level

Single-ended high speed channel

AVCC − 10

AVCC + 10

mV

Low Voltage Level

Single-ended high speed channel

AVCC − 600

AVCC − 400

mV

Rise/Fall Time (20% to 80%)

75

135

200

ps

INPUT TERMINATION

Resistance

Single-ended

50

Ω

AUXILIARY CHANNELS

100

Ω

DC bias = 2.5 V, ac voltage = 3.5 V, f = 100 kHz

8

pF

Input/Output Voltage Range

DVEE

AMUXVCC

V

POWER SUPPLY

AVCC

Operating range

3

3.3

3.6

V

QUIESCENT CURRENT

AVCC

Outputs disabled

30

40

45

mA

Outputs enabled, no pre-emphasis

53

60

66

mA

Outputs enabled, maximum pre-emphasis

98

108

120

mA

VTTI

Input termination on4

5

40

54

mA

VTTO

Output termination on, no pre-emphasis

36

40

44

mA

Output termination on, maximum

pre-emphasis

73

80

88

mA

DVCC

4

7

10

mA

AMUXVCC

0.01

0.1

mA

POWER DISSIPATION

Outputs disabled

115

271

364

mW

Outputs enabled, no pre-emphasis

411

574

664

mW

Outputs enabled, maximum pre-emphasis

754

936

1057

mW

TIMING CHARACTERISTICS

Switching/Update Delay

High speed switching register: HS_CH

200

ms

All other configuration registers

1.5

μs

RESET Pulse Width

50

ns