AM29SL400DB120WAC datasheet(4/41 Pages) SPANSION

部件名	AM29SL400DB120WAC

功能描述	4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory

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制造商	SPANSION [SPANSION]

网页	http://www.spansion.com

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Am29SL400D

Rev. A Amend. +1 April 13, 2005

ADV ANCE

I N FO RMAT I O N

GENERAL DESCRIPTION

The Am29SL400D is an 4Mbit, 1.8 V volt-only Flash

memory organized as 524,288 bytes or 262,144 words.

The device is offered in a 48-ball FBGA package. The

word-wide data (x16) appears on DQ15–DQ0; the

byte-wide (x8) data appears on DQ7–DQ0. This device

is designed to be programmed and erased in-system

with a single 1.8 volt VCC supply. No VPP is required for

write or erase operations. The device can also be pro-

grammed in standard EPROM programmers.

The standard device offers access times of 90, 100,

and 120 ns, allowing high speed microprocessors to

operate without wait states. To eliminate bus contention

the device has separate chip enable (CE#), write

enable (WE#) and output enable (OE#) controls.

The device requires only a single 1.8 volt power

supply for both read and write functions. Internally

generated and regulated voltages are provided for the

program and erase operations.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Com-

mands are written to the command register using stan-

dard microprocessor write timings. Register contents

serve as input to an internal state-machine that con-

trols the erase and programming circuitry. Write cycles

also internally latch addresses and data needed for the

programming and erase operations. Reading data out

of the device is similar to reading from other Flash or

EPROM devices.

Device programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin. The Unlock Bypass mode facili-

tates faster programming times by requiring only two

write cycles to program data instead of four.

Device erasure o ccu rs by executin g th e era se

command sequence. This initiates the Embedded

Erase algorithm—an internal algorithm that automati-

cally preprograms the array (if it is not already pro-

grammed) before executing the erase operation.

During erase, the device automatically times the erase

pulse widths and verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by observing the RY/BY#

pin, or by reading the DQ7 (Data# Polling) and DQ6

(toggle) status bits. After a program or erase cycle has

been completed, the device is ready to read array data

or accept another command.

The sector erase architecture allows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection measures include a low

VCC detector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of

memory. This can be achieved in-system or via pro-

gramming equipment.

The Erase Suspend feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operation

in progress and resets the internal state machine to

reading array data. The RESET# pin may be tied to the

system reset circuitry. A system reset would thus also

reset the device, enabling the system microprocessor

to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When

addresses have been stable for a specified amount of

time, the device enters the automatic sleep mode.

The system can also place the device into the standby

mode. Power consumption is greatly reduced in both

these modes.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effectiveness.

The device electrically erases all bits within a sector

simultaneously via Fowler-Nordheim tunneling. The

data is programmed using hot electron injection.

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Advanced Micro Devices	AM29SL400DB120WAC	776Kb / 41P	4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory

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Advanced Micro Devices	AM29SL400C	846Kb / 44P	4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory
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