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AM29PDS322DT10WMI 数据表(PDF) 11 Page - SPANSION |
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AM29PDS322DT10WMI 数据表(HTML) 11 Page - SPANSION |
11 / 51 page December 4, 2006 23569A5 Am29PDS322D 9 D A TA SH EET Page Mode Read The device is capable of fast Page mode read and is compatible with the Page mode Mask ROM read oper- ation. This mode provides faster read access speed for random locations within a page. The Page size of the device is 4 words. The appropriate Page is selected by the higher address bits A20–A2 and the LSB bits A1–A0 determine the specific word within that page. This is an asynchronous operation with the micropro- cessor supplying the specific word location. The random or initial page access is equal to t ACC or t CE and subsequent Page read accesses (as long as the locations specified by the microprocessor falls within that Page) are equivalent to t PACC. When CE# is deasserted and reasserted for a subsequent access, the access time is t ACC or tCE. Here again, CE# selects the device and OE# is the output control and should be used to gate data to the output pins if the device is se- lected. Fast Page mode accesses are obtained by keeping A2–A20 constant and changing A0 to A1 to select the specific word within that page. See Figure 16 for timing specifications. The following table determines the specific word within the selected page: Table 2. Page Word Mode Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V IL, and OE# to VIH. The device features an Unlock Bypass mode to facili- tate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are re- quired to program a word, instead of four. The “Word Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Table 2 indicates the address space that each sector occupies. I CC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is prima- rily intended to allow faster manufacturing throughput at the factory. If the system asserts V HH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the ACC pin returns the device to normal op- eration. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose- lect Command Sequence sections for more informa- tion. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be sus- pended to read from or program to another location within the same bank (except the sector being erased). Figure 21 shows how read and write cycles may be initiated for simultaneous operation with zero latency. I CC6 and ICC7 in the DC Characteristics table represent the current specifications for read-while-pro- gram and read-while-erase, respectively. Standby Mode When the system is not reading or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V CC ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at VIH, but not within V CC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device re- quires standard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data. Word A1 A0 Word 0 0 0 Word 1 0 1 Word 2 1 0 Word 3 1 1 |
类似零件编号 - AM29PDS322DT10WMI |
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类似说明 - AM29PDS322DT10WMI |
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