ADF4156

Rev. 0 | Page 2 of 24

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 4

Absolute Maximum Ratings............................................................ 5

Thermal Impedance ..................................................................... 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

Typical Performance Characteristics ............................................. 7

Circuit Description........................................................................... 8

Reference Input Section............................................................... 8

RF Input Stage............................................................................... 8

RF INT Divider............................................................................. 8

INT, FRAC, MOD, and R Relationship ..................................... 8

RF R Counter ................................................................................ 8

Phase Frequency Detector (PFD) and Charge Pump.............. 9

MUXOUT and LOCK Detect..................................................... 9

Input Shift Registers ..................................................................... 9

Program Modes ............................................................................ 9

Register Maps.................................................................................. 10

FRAC/INT Register, R0............................................................. 11

PHASE REGISTER, R1.............................................................. 12

MOD/R Register, R2 .................................................................. 13

Function Register, R3................................................................. 15

CLK Div Register, R4 ................................................................. 16

Reserved Bits............................................................................... 16

Initialization Sequence .............................................................. 16

RF Synthesizer: A Worked Example ........................................ 17

Modulus....................................................................................... 17

Reference Doubler and Reference Divider ............................. 17

12-Bit Programmable Modulus................................................ 17

Cycle Slip Reduction for Faster Lock Times........................... 17

Spur Mechanisms ....................................................................... 18

Spur Consistency and Fractional Spur Optimization ........... 18

PHASE RESYNC ........................................................................ 19

Low Frequency Applications .................................................... 19

Filter Design—ADIsimPLL....................................................... 19

Interfacing ................................................................................... 20

PCB Design Guidelines for Chip Scale Package .................... 20

Outline Dimensions ....................................................................... 21

Ordering Guide .......................................................................... 22

REVISION HISTORY

5/06—Revision 0: Initial Version