MC145483

MOTOROLA

4

connected to the VAG voltage. This minimizes transients at

the RO– pin when full–channel operation is resumed by

clocking the FSR pin. This pin is high impedance when the

device is in the powered–down mode.

PI

Power Amplifier Input (Pin 3)

This is the inverting input to the PO– amplifier. The non–

inverting input to the PO– amplifier is internally tied to the

VAG pin. The PI and PO– pins are used with external resis-

tors in an inverting op amp gain circuit to set the gain of the

PO+ and PO– push–pull power amplifier outputs. Connect-

ing PI to VDD will power down the power driver amplifiers and

the PO+ and PO– outputs will be high impedance.

PO–

Power Amplifier Output (Inverting) (Pin 4)

This is the inverting power amplifier output, which is used

to provide a feedback signal to the PI pin to set the gain of

the push–pull power amplifier outputs. This pin is capable of

driving a 300

Ω load to PO+. The PO+ and PO– outputs are

differential (push–pull) and capable of driving a 300

Ω load to

1.772 V peak, which is 3.544 V peak–to–peak. The bias volt-

age and signal reference of this output is the VAG pin. The

VAG pin cannot source or sink as much current as this pin,

and therefore low impedance loads must be between PO+

and PO–. The PO+ and PO– differential drivers are also ca-

pable of driving a 100

Ω resistive load or a 100 nF Piezoelec-

tric transducer in series with a 20

Ω resister with a smalll

increase in distortion. These drivers may be used to drive re-

sistive loads of

≥ 32 Ω when the gain of PO– is set to 1/4 or

less. Connecting PI to VDD will power down the power driver

amplifiers, and the PO+ and PO– outputs will be high imped-

ance. This pin is also high impedance when the device is

powered down by the PDI pin.

PO+

Power Amplifier Output (Non–Inverting) (Pin 5)

This is the non–inverting power amplifier output, which is

an inverted version of the signal at PO–. This pin is capable

of driving a 300

Ω load to PO–. Connecting PI to VDD will

power down the power driver amplifiers and the PO+ and

PO– outputs will be high impedance. This pin is also high im-

pedance when the device is powered down by the PDI pin.

See PI and PO– for more information.

DIGITAL INTERFACE

MCLK

Master Clock (Pin 11)

This is the master clock input pin. The clock signal applied

to this pin is used to generate the internal 256 kHz clock and

sequencing signals for the switched–capacitor filters, ADC,

and DAC. The internal prescaler logic compares the clock on

this pin to the clock at FST (8 kHz) and will automatically

accept 256, 512, 1536, 1544, 2048, 2560, or 4096 kHz. For

MCLK frequencies of 256 and 512 kHz, MCLK must be syn-

chronous and approximately rising edge aligned to FST. For

optimum performance at frequencies of 1.536 MHz and

higher, MCLK should be synchronous and approximately ris-

ing edge aligned to the rising edge of FST. In many ap-

plications, MCLK may be tied to the BCLKT pin.

FST

Frame Sync, Transmit (Pin 14)

This pin accepts an 8 kHz clock that synchronizes the out-

put of the serial PCM data at the DT pin. This input is com-

patible with both Long Frame Sync and Short Frame Sync. If

both FST and FSR are held low for several 8 kHz frames, the

device will power down. FST must be clocking for the device

to power up affter being powered down by the frame syncs.

BCLKT

Bit Clock, Transmit (Pin 12)

This pin controls the transfer rate of transmit PCM data. In

the synchronous modes of sign–bit extended and receive

gain adjust, the BCLKT also controls the transfer rate of the

receive PCM data. This pin can accept any bit clock frequen-

cy from 256 to 4096 kHz for Long Frame Sync and Short

Frame Sync timing.

DT

Data, Transmit (Pin 13)

This pin is controlled by FST and BCLKT and is high im-

pedance except when outputting PCM data. This pin is high

impedance when the device is in the powered–down mode.

FSR

Frame Sync, Receive (Pin 7)

This pin accepts an 8 kHz clock, which synchronizes the

input of the serial PCM data at the DR pin. FSR can be

asynchronous to FST in the Long Frame Sync or Short

Frame Sync modes.

BCLKR

Bit Clock, Receive (Pin 9)

This pin accepts any bit clock frequency from 256 to 4096

kHz. The BCLKR pin is also used as a mode select pin when

not being clocked for several 8 kHz frames. The BCKLT pin

is used to clock the receive PCM data transfers when the

BCLKR pin is not being clocked. When the BCLKR pinis a

logic 0, the sign–bit extended synchronous mode is selected,

which uses 16–bit transfers with the first four bits being the

sign bit. When the BCLKR pin is a logic 1, the receive gain

adjust synchronous mode is selected, which uses a 13–bit

transfer for the transmit PCM data, but uses a 16–bit transfer

for the receive side, with the 13–bit voice data being first, fol-

lowed by three bits which control the attenuation of the re-

ceive analog output.

DR

Data, Receive (Pin 8)

This pin is the PCM data input. See the pin descriptions for

FSR, BCLKR, and BCKLT for more information.