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AD5744 数据表(PDF) 11 Page - Analog Devices

部件名 AD5744
功能描述  Complete, Quad, 14/16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD5744 数据表(HTML) 11 Page - Analog Devices

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Preliminary Technical Data
Rev. PrA 15-Nov-04| Page 11 of 27
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD5744/64
TOP VIEW
(Not to Scale)
SYNC
SCLK
SDIN
SDO
CLR
LDAC
D1
D0
AGNDA
VOUTA
VOUTB
AGNDB
AGNDC
VOUTC
VOUTD
AGNDD
1
32
25
916
8
24
17
PIN 1
INDICATOR
Figure 6. 32-Lead TQFP Pin Configuration Diagram
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Function
1
SYNC
Active Low Input. This is the frame synchronization signal for the serial interface.
While SYNC is low, data is transferred in on the falling edge of SCLK.
2
SCLK13
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK.
This operates at clock speeds up to 30 MHz.
3
SDIN13
Serial Data Input. Data must be valid on the falling edge of SCLK.
4
SDO
Serial Data Output. Used to clock data from the serial register in daisy-chain or
readback mode.
5
CLR13
Active Low Input. Asserting this pin sets the DAC registers to 0x0000.
6
LDAC
Load DAC. Logic input. This is used to update the DAC registers and consequently
the analog output. When tied permanently low, the addressed DAC register is
updated on the 24th clock of the serial register write. If LDAC is held high during the
write cycle, the DAC input register is updated but the output is held off until the
falling edge of LDAC. In this mode, all analog outputs can be updated
simultaneously on the falling edge of LDAC.
7, 8
D0, D1
D0 and D1 form a digital I/O port. The user can configure these pins as inputs or
outputs that are configurable and readable over the serial interface. When
configured as inputs, these pins have weak internal pull-ups to DVCC.
9
RSTOUT
Reset Logic Output. This is the output from the on-chip voltage monitor used in the
reset circuit. If desired, it may be used to control other system components.
10
RSTIN
Reset Logic Input. This input allows external access to the internal reset logic.
Applying a Logic 0 to this input resets the DAC output to 0 V. In normal operation,
RSTIN should be tied to Logic 1.
11
DGND
Digital GND Pin.
12
DVCC
Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V. When programmed as
outputs, D0 and D1 are referenced to DVCC.
13, 31
AVDD
Positive Analog Supply Pins. Voltage ranges from 11.4 V to 16.5 V.
14
PGND
Ground Reference Point for Analog Circuitry.
15, 30
AVSS
Negative Analog Supply Pins. Voltage ranges from –11.4 V to –16.5 V.
13 Internal pull-up device on this logic input. Therefore, it can be left floating and will default to a logic high condition.
AD5744/AD5764


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