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74LVC74AD 数据表(PDF) 6 Page - NXP Semiconductors

部件名 74LVC74AD
功能描述  Dual D-type flip-flop with set and reset; positive-edge trigger
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制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
标志 PHILIPS - NXP Semiconductors

74LVC74AD 数据表(HTML) 6 Page - NXP Semiconductors

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Dual D-type flip-flop with set and reset;
positive-edge trigger
Philips Semiconductors
Product Specification
74LVC74A
1998 Jun 17
6
AC WAVEFORMS
VM = 1.5 V at VCC w 2.7 V
VM = 0.5 S VCC at VCC < 2.7 V
VOL and VOH are the typical output voltage drop that occur with the
output load.
SV00489
VM
nD INPUT
nCP INPUT
nQ OUTPUT
nQ OUTPUT
VM
VM
VM
t su
t su
1/f max
t h
th
t PHL
t PHL
t PLH
t PLH
tW
GND
GND
VI
VI
VOL
VOL
VOH
VOH
NOTE: The shaded areas indicate when the inputis permitted to change for predictable
output performance.
Figure 1. Clock (nCP) to output (nQ, nQ) propagation delays,
clock pulse width, nD to nCP set-up times,
the nCP to nD hold times, output transition times
and maximum clock pulse frequency.
SV00490
VM
nCP INPUT
nS D INPUT
nR D INPUT
nQ OUTPUT
nQ OUTPUT
VM
VM
VM
trem
tPHL
tPLH
tW
tW
VM
tPHL
tPLH
GND
GND
GND
VI
VI
VI
VOL
VOL
VOH
VOH
Figure 2. Set (nSD) and reset (nRD) input to output (nQ, nQ)
propagation delays, the set and reset pulse widths
and the nRD to nCP removal time.
TEST CIRCUIT
SWITCH POSITION
PULSE
GENERATOR
RT
VI
D.U.T.
VO
CL
VCC
500
Open
GND
S1
VCC
VI
< 2.7V
VCC
TEST
S1
tPLH/tPHL
Open
2.7V
2.7–3.6V
50pF
500
2 * VCC
SV00903
Figure 3. Load circuitry for switching times.


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