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74LVC161DB 数据表(PDF) 9 Page - NXP Semiconductors

部件名 74LVC161DB
功能描述  Presettable synchronous 4-bit binary counter; asynchronous reset
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制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
标志 PHILIPS - NXP Semiconductors

74LVC161DB 数据表(HTML) 9 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74LVC161
Presettable synchronous 4-bit binary counter;
asynchronous reset
1998 May 20
9
AC WAVEFORMS
VM = 1.5 V at VCC w 2.7 V
VM = 0.5 S VCC at VCC < 2.7 V
VOL and VOH are the typical output voltage drop that occur with the
output load.
VM
VM
1/fMAX
tw
tPLH
tPHL
CP INPUT
Qn, TC OUTPUT
SY00071
GND
VI
VOH
VOL
Waveform 1.
Clock (CP) to outputs (Qn, TC) propagation
delays, the clock pulse width and the maximum clock
frequency.
VM
tPLH
tPHL
CET INPUT
TC OUTPUT
VM
VI
GND
VOH
VOL
SY00072
Waveform 2.
Input (CET) to output (TC) propagation delays.
VM
VM
tw
trem
tPHL
MR INPUT
Qn, TC OUTPUT
GND
VI
VOH
VOL
SY00073
CP INPUT
GND
VI
Waveform 3.
Master reset (MR) pulse width, the master reset
to output (Qn, TC) propagation delays and the master reset to
clock (CP) removal times.
The shaded areas indicate when the input is permitted
to change for predictable output performance.
th
th
VM
VM
VM
VI
VI
VI
GND
GND
GND
PE INPUT
CP INPUT
Dn INPUT
tSU
tSU
th
tSU
th
tSU
SC00137
Waveform 4.
Setup and hold times for the input (Dn) and
parallel enable input (PE).
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
VM
VM
VM
tsu
th
tsu
th
SC00138
VI
VI
GND
GND
CEP, CET
INPUT
CP INPUT
Waveform 5.
CEP and CET setup and hold times.
TEST CIRCUIT
SWITCH POSITION
PULSE
GENERATOR
RT
VI
D.U.T.
VO
CL
VCC
500
Open
GND
S1
VCC
VI
< 2.7V
VCC
TEST
S1
tPLH/tPHL
Open
2.7V
2.7–3.6V
50pF
500
2 * VCC
SV00903
Waveform 6.
Load circuitry for switching times.


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