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74LV74D 数据表(PDF) 7 Page - NXP Semiconductors |
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74LV74D 数据表(HTML) 7 Page - NXP Semiconductors |
7 / 12 page Philips Semiconductors Product specification 74LV74 Dual D-type flip-flop with set and reset; positive edge-trigger 1998 Apr 20 7 AC WAVEFORMS VM = 1.5V at VCC w 2.7V v 3.6V VM = 0.5 * VCC at VCC t 2.7V and w 4.5V VOL and VOH are the typical output voltage drop that occur with the output load. nQ OUTPUT VM nD INPUT nCP INPUT nQ OUTPUT VM VM VM tsu 1/fmax th th tPHL tPHL tPLH tPLH tW GND GND VI VI VOL VOL VOH VOH tsu SV00335 Figure 1.The clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP setup times, the nCP to nD hold times, the output transition times and the maximum clock pulse frequency NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. nCP INPUT nSD INPUT nRD INPUT nQ OUTPUT nQ OUTPUT GND GND GND VI VI VI VOL VOL VOH VOH VM VM VM VM trem tPHL tPLH tW tW VM tPLH tPHL SV00336 Figure 2.The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths and the nRD to nCP removal time TEST CIRCUIT PULSE GENERATOR RT Vl D.U.T. VO CL RL= 1k Vcc Test Circuit for Outputs DEFINITIONS VCC VI < 2.7V 2.7–3.6V VCC 2.7V TEST tPLH/tPHL ≥ 4.5 V VCC RL = Load resistor CL = Load capacitance includes jig and probe capacitiance 50pF RT = Termination resistance should be equal to ZOUT of pulse generators. SV00902 Figure 3. Load circuitry for switching times |
类似零件编号 - 74LV74D |
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类似说明 - 74LV74D |
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