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74HCT377PW 数据表(PDF) 7 Page - NXP Semiconductors |
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74HCT377PW 数据表(HTML) 7 Page - NXP Semiconductors |
7 / 7 page December 1990 7 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger 74HC/HCT377 AC WAVEFORMS PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. Fig.6 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, output transition times and the maximum clock pulse frequency. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the data set-up and hold times from the data input (Dn) and from the data enable input (E) to the clock (CP). The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. |
类似零件编号 - 74HCT377PW |
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类似说明 - 74HCT377PW |
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