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74HC40105N 数据表(PDF) 10 Page - NXP Semiconductors |
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74HC40105N 数据表(HTML) 10 Page - NXP Semiconductors |
10 / 25 page 1998 Jan 23 10 Philips Semiconductors Product specification 4-bit x 16-word FIFO register 74HC/HCT40105 tW SI pulse width HIGH or LOW 16 6 20 24 ns 4.5 Fig.6 tW SO pulse width HIGH or LOW 16 7 20 24 ns 4.5 Fig.9 tW DIR pulse width HIGH or LOW 6 20 34 5 43 5 51 ns 4.5 Fig.7 tW DOR pulse width HIGH or LOW 6 19 34 5 43 5 51 ns 4.5 Fig.9 tW MR pulse width HIGH 16 7 20 24 ns 4.5 Fig.8 trem removal time MR to SI 15 7 19 22 ns 4.5 Fig.15 tsu set-up time Dn to SI −5 −14 −4 −4 ns 4.5 Fig.13 th hold time Dn to SI 27 16 34 41 ns 4.5 Fig.13 fmax maximum pulse frequency SI, SO using flags or burst mode 28 12 10 MHz 4.5 Fig.6, 9, 11 and 12 fmax maximum pulse frequency SI, SO cascaded 28 12 10 MHz 4.5 Figs 6 and 9 SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HCT VCC (V) WAVEFORMS +25 −40 to +85 −40 to +125 min. typ. max. min. max. min. max. |
类似零件编号 - 74HC40105N |
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类似说明 - 74HC40105N |
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