September 1993

2

Philips Semiconductors

Product specification

Octal D-type flip-flop with reset;

positive-edge trigger

74HC/HCT273

FEATURES

• Ideal buffer for MOS microprocessor or memory

• Common clock and master reset

• Eight positive edge-triggered D-type flip-flops

• See “377” for clock enable version

• See “373” for transparent latch version

• See “374” for 3-state version

• Output capability; standard

GENERAL DESCRIPTION

The 74HC/HCT273 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT273 have eight edge-triggered, D-type

flip-flops with individual D inputs and Q outputs. The

common clock (CP) and master reset (MR) inputs load and

reset (clear) all flip-flops simultaneously.

The state of each D input, one set-up time before the

LOW-to-HIGH clock transition, is transferred to the

All outputs will be forced LOW independently of clock or

data inputs by a LOW voltage level on the MR input.

The device is useful for applications where the true output

only is required and the clock and master reset are

common to all storage elements.

QUICK REFERENCE DATA

Notes

ORDERING INFORMATION

See

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HC

HCT

propagation delay

15

15

ns

15

20

ns

maximum clock frequency

66

36

MHz

input capacitance

3.5

3.5

pF

power dissipation capacitance per flip-flop

notes 1 and 2

20

23

pF