December 1990

2

Philips Semiconductors

Product specification

3-to-8 line decoder/demultiplexer with

address latches

74HC/HCT237

FEATURES

• Combines 3-to-8 decoder with 3-bit latch

• Multiple input enable for easy expansion or independent

controls

• Active HIGH mutually exclusive outputs

• Output capability: standard

GENERAL DESCRIPTION

The 74HC/HCT237 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT237 are 3-to-8 line decoder/demultiplexers

essentially combines the 3-to-8 decoder function with a

3-bit storage latch. When the latch is enabled (LE = LOW),

the “237” acts as a 3-to-8 active LOW decoder. When the

latch enable (LE) goes from LOW-to-HIGH, the last data

present at the inputs before this transition, is stored in the

latches. Further address changes are ignored as long as

LE remains HIGH.

the outputs independent of the address inputs or latch

is HIGH.

The “237” is ideally suited for implementing

non-overlapping decoders in 3-state systems and strobed

(stored address) applications in bus oriented systems.

QUICK REFERENCE DATA

Notes

ORDERING INFORMATION

See

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HC

HCT

propagation delay

16

19

ns

19

21

ns

14

17

ns

14

17

ns

input capacitance

3.5

3.5

pF

power dissipation capacitance per package

notes 1 and 2

60

63

pF