数据搜索系统,热门电子元器件搜索 |
|
74F8961 数据表(PDF) 1 Page - NXP Semiconductors |
|
74F8961 数据表(HTML) 1 Page - NXP Semiconductors |
1 / 11 page Philips Semiconductors FAST Products Product specification 74F8960/74F8961 Octal latched bidirectional Futurebus transceivers (3-State + open-collector) 1 December 19, 1990 853-1120 01322 FEATURES • Octal latched transceiver • Drives heavily loaded backplanes with equivalent load impedances down to 10 Ω • High drive (100mA) open collector drivers on B port • Reduced voltage swing (1 volt) produces less noise and reduces power consumption • High speed operation enhances performance of backplane buses and facilitates incident wave switching • Compatible with IEEE futurebus standards • Built-in precision band-gap reference provides accurate receiver thresholds and improved noise immunity • Controlled output ramp and multiple GND pins minimize ground bounce • Glitch-free power up/down operation DESCRIPTION The 74F8960 and 74F8961 are octal bidirectional latched transceivers and are intended to provide the electrical interface to a high performance wired–OR bus. The B port inverting drivers are low–capacitance open collector with controlled ramp and are designed to sink 100mA from 2 volts. The B port inverting receivers have a 100 mV threshold region and a 4ns glitch filter. The B port interfaces to ‘Backplane Transceiver Logic’ (BTL). BTL features a reduced (1V to 2V) voltage swing for lower power consumption and a series diode on the drivers to reduce capacitive loading. Incident switching is employed, therefore BTL propagation delays are short. Although the voltage swing is much less for BTL, so is its receiver threshold region, therefore noise margins are excellent. BTL offers low power consumption, low ground bounce, EMI and crosstalk, low capacitive loading, superior noise margin and low propagation delays. This results in a high bandwidth, reliable backplane. The 74F8960 and 74F8961 A ports have TTL 3–state drivers and TTL receivers with a latch function. A separate High–level control input (VX) is provided to limit the A side output level to a given voltage level (such as 3.3V). For 5.0V systems, VX is simply tied to VCC. The 74F8961 is the non–inverting version of 74F8960. TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT( TOTAL) 74F8960 6.5ns 80mA 74F8961 6.5ns 80mA ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 28–pin plastic DIP (300 mil)1 N74F8960N, N748961N 28–pin PLCC1 N74F8960A, N74F8961A NOTE: Thermal mounting techiques are recommended. INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW A0 – A8 PNP latched inputs 3.5/0.117 70 µA/70µA B0 – B8 Data inputs with threshold circuitry 5.0/0.167 100 µA/100µA OEA A output enable input (active high) 1.0/0.033 20 µA/20µA OEB0, OEB1 B output enable inputs (active low) 1.0/0.033 20 µA/20µA LE Latch enable input (active low) 1.0/0.033 20 µA/20µA A0 – A7 3–state outputs 150/40 3mA/24mA B0 – B7 Open collector outputs OC/166.7 OC/100mA NOTES: 1. One (1.0) FAST unit load is defined as: 20 µA in the high state and 0.6mA in the low state. 2. OC = Open collector. |
类似零件编号 - 74F8961 |
|
类似说明 - 74F8961 |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |