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74F175AN 数据表(PDF) 5 Page - NXP Semiconductors |
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74F175AN 数据表(HTML) 5 Page - NXP Semiconductors |
5 / 10 page Philips Semiconductors Product specification 74F175A Quad D flip-flop 1996 Mar 12 5 AC SETUP REQUIREMENTS FOR 74F175A LIMITS Tamb = 25°C Tamb = 0°C to +70°C Tamb = *40°C to +85°C SYMBOL PARAMETER TEST VCC = +5V VCC = +5.0V ± 10% VCC = +5.0V ± 10% UNIT CONDITION CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω MIN TYP MAX MIN MAX MIN MAX ts(H) ts(L) Setup time, High or Low Dn to CP Waveform 2 3.0 3.0 3.5 3.5 4.0 4.0 ns th(H) th(L) Hold time, High or Low Dn to CP Waveform 2 0.0 0.0 0.0 0.0 0.0 0.0 ns tw(H) tw(L) CP Pulse width High or Low Waveform 1 3.0 4.0 3.5 5.0 4.0 5.5 ns tw(L) MR Pulse width Low Waveform 3 3.5 3.5 4.0 ns tREC Recovery time MR to CP Waveform 3 4.0 4.5 5.0 ns AC WAVEFORMS For all waveforms, VM = 1.3V. CP VM VM VM tw(H) 1/fmax VM VM tPLH tw(L) tPHL Qn VM VM Qn tPLH tPHL SF00722 Waveform 1. Propagation delay for clock input to output, clock pulse width, and maximum clock frequency th(H) ts(H) CP SF00191 VM VM VM VM VM VM th(L) ts(L) Dn Waveform 2. Data setup time and hold times CP VM VM VM VM tPHL tREC MR Qn tw(L) VM Qn tPLH SF00723 Waveform 3. Master Reset pulse width, Master Reset to output delay and Master Reset to Clock recovery time |
类似零件编号 - 74F175AN |
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类似说明 - 74F175AN |
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