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74ALVCH16374DGG 数据表(PDF) 2 Page - NXP Semiconductors |
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74ALVCH16374DGG 数据表(HTML) 2 Page - NXP Semiconductors |
2 / 12 page Philips Semiconductors Product specification 74ALVCH16374 16-bit edge-triggered D-type flip-flop (3-State) 2 1998 Jun 18 853-2073 19604 FEATURES • Wide supply voltage range of 1.2 V to 3.6 V • Complies with JEDEC standard no. 8-1A • CMOS low power consumption • MULTIBYTETM flow-through standard pin-out architecture • Low inductance multiple V CC and ground pins for minimum noise and ground bounce • Direct interface with TTL levels • All data inputs have bushold • Output drive capability 50Ω transmission lines @ 85°C • Current drive ±24 mA at 3.0 V DESCRIPTION The 74ALVCH16374 is a 16-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-State outputs for bus oriented applications. Incorporates bus hold data inputs which eliminate the need for external pull-up or pull-down resistors to hold unused inputs. The 74ALVCH16374 consists of 2 sections of eight edge-triggered flip-flops. A clock (CP) input and an output enable (OE) are provided per 8-bit section. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 1OE 1Q0 1Q1 GND 1Q2 1Q3 VCC 1Q5 GND 1Q6 1Q7 2Q0 2Q1 GND 1Q4 2Q2 2Q3 VCC 2Q4 2Q5 2D5 2D4 VCC 2D3 2D2 GND 2D1 2D0 1D7 1D6 GND 1D5 1D4 VCC 1D3 1D2 GND 1D1 1D0 1CP 21 22 23 24 25 26 27 28 GND 2Q6 2Q7 2OE 2CP 2D7 2D6 GND SW00074 QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT t /t Propagation delay VCC = 2.5V, CL = 30pF 2.3 ns tPHL/tPLH gy CP to Qn VCC = 3.3V, CL = 50pF 2.4 ns f Maximum clock frequency VCC = 2.5V 300 MHz fMAX Maximum clock frequency VCC = 3.3V 350 MHz CI Input capacitance 5.0 pF C Power dissipation capacitance per flip flop V = GND to VCC1 Outputs enabled 16 pF CPD Power dissipation capacitance per flip-flop VI = GND to VCC1 Outputs disabled 10 pF NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 48-Pin Plastic SSOP Type III –40 °C to +85°C 74ALVCH16374 DL ACH16374 DL SOT370-1 48-Pin Plastic TSSOP Type II –40 °C to +85°C 74ALVCH16374 DGG ACH16374 DGG SOT362-1 |
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类似说明 - 74ALVCH16374DGG |
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