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74AHCT74PW 数据表(PDF) 8 Page - NXP Semiconductors |
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74AHCT74PW 数据表(HTML) 8 Page - NXP Semiconductors |
8 / 20 page 1999 Sep 23 8 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74AHC74; 74AHCT74 AC CHARACTERISTICS Type 74AHC74 GND = 0 V; tr =tf ≤ 3.0 ns. SYMBOL PARAMETER TEST CONDITIONS Tamb (°C) UNIT WAVEFORMS CL 25 −40 to +85 −40 to +125 MIN. TYP. MAX. MIN. MAX. MIN. MAX. VCC = 3.0 to 3.6 V; note 1 tPHL/tPLH propagation delay nCP to nQ, nQ see Figs 6 and 8 15 pF − 5.2 11.9 1.0 14.0 1.0 15.0 ns propagation delay nSD nRD to nQ, nQ see Figs 7 and 8 − 5.4 12.3 1.0 14.5 1.0 15.5 ns fmax maximum clock pulse frequency 80 125 − 45 − 45 − ns tPHL/tPLH propagation delay nCP to nQ, nQ see Figs 6 and 8 50 pF − 7.4 15.4 1.0 17.5 1.0 19.5 ns propagation delay nSD nRD to nQ, nQ see Figs 7 and 8 − 7.7 15.8 1.0 18.0 1.0 20.0 ns tW clock pulse width HIGH or LOW see Figs 6 and 8 6.0 −− 7.0 − 7.0 − ns set or reset pulse width LOW see Figs 7 and 8 6.0 −− 7.0 − 7.0 − ns trem removal time set or reset 5.0 −− 5.0 − 5.0 − ns tsu set-up time nD to nCP see Figs 6 and 8 6.0 −− 7.0 − 7.0 − ns th hold time nD to nCP 0.5 −− 0.5 − 0.5 − ns fmax maximum clock pulse frequency 50 75 − 70 − 70 − ns |
类似零件编号 - 74AHCT74PW |
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类似说明 - 74AHCT74PW |
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