Philips Semiconductors

Product specification

74ABT899

9-bit dual latch transceiver with 8-bit parity

generator/checker (3-State)

1998 Jan 16

6

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

LIMITS

UNIT

Min

Max

DC supply voltage

4.5

5.5

V

Input voltage

0

V

High-level input voltage

2.0

V

Low-level Input voltage

0.8

V

High-level output current

–32

mA

Low-level output current

64

mA

∆t/∆v

Input transition rise or fall rate

0

5

ns/V

Operating free-air temperature range

–40

+85

°C

DC ELECTRICAL CHARACTERISTICS

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

to +85

°C

UNIT

Min

Typ

Max

Min

Max

Input clamp voltage

–0.9

–1.2

–1.2

V

2.5

3.5

2.5

V

High-level output voltage

3.0

4.0

3.0

V

2.0

2.6

2.0

V

Low-level output voltage

0.42

0.55

0.55

V

Power-up output low

0.13

0.55

0.55

V

Input leakage

Control pins

±0.01

±1.0

±1.0

µA

current

Data pins

±5

±100

±100

µA

Power-off leakage current

±5.0

±100

±100

µA

Power-up/down 3-State

±5.0

±50

±50

µA

3-State output High current

5.0

50

50

µA

3-State output Low current

–5.0

–50

–50

µA

Output High leakage current

5.0

50

50

µA

–50

–80

–180

–50

–180

mA

50

250

250

µA

Quiescent supply current

28

34

34

mA

50

250

250

µA

Additional supply current per

0.3

1.5

1.5

mA

NOTES:

1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

2. This is the increase in supply current for each input at 3.4V.

3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.

transition time of up to 100

µsec is permitted.