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74ABT74 数据表(PDF) 1 Page - NXP Semiconductors

部件名 74ABT74
功能描述  Dual D-type flip-flop
Download  5 Pages
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制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
标志 PHILIPS - NXP Semiconductors

74ABT74 数据表(HTML) 1 Page - NXP Semiconductors

  74ABT74 Datasheet HTML 1Page - NXP Semiconductors 74ABT74 Datasheet HTML 2Page - NXP Semiconductors 74ABT74 Datasheet HTML 3Page - NXP Semiconductors 74ABT74 Datasheet HTML 4Page - NXP Semiconductors 74ABT74 Datasheet HTML 5Page - NXP Semiconductors  
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Philips Semiconductors
Product specification
74ABT74
Dual D-type flip-flop
1
853-1813 15793
1995 Sep 22
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
Tamb = 25°C;
GND = 0V
TYPICAL
UNIT
tPLH
tPHL
Propagation
delay
CPn to
Qn, Qn
CL = 50pF;
VCC = 5V
3.0
2.5
ns
tOSLH
tOSHL
Output to
Output skew
CC
0.5
ns
CIN
Input
capacitance
VI = 0V or VCC
3
pF
ICC
Total supply
current
Outputs disabled;
VCC = 5.5V
50
µA
PIN CONFIGURATION
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND
VCC
SD1
Q1
Q1
CP1
RD1
D1
RD1
D0
Q0
CP0
SD1
Q0
SF00045
PIN DESCRIPTION
PIN NUMBER
SYMBOL
NAME AND FUNCTION
1, 2, 3, 4, 10,
11, 12, 13
RDn, Dn,
CPn, SDn
Data inputs
5, 6, 8, 9
Qn, Qn
Data outputs
7
GND
Ground (0V)
14
VCC
Positive supply voltage
LOGIC SYMBOL
Q0 Q0Q1 Q1
56
98
VCC = Pin 14
GND = Pin 7
3
4
1
11
10
13
CP0
SD0
RD0
CP1
SD1
RD1
D0
D1
212
SA00359
DESCRIPTION
The 74ABT74 is a dual positive edge-triggered D-type flip-flop
featuring individual data, clock, set, and reset inputs; also true and
complementary outputs. Set (SD) and reset (RD) are asynchronous
active low inputs and operate independently of the clock input.
When set and reset are inactive (high), data at the D input is
transferred to the Q and Q outputs on the low-to-high transition of
the clock. Data must be stable just one setup time prior to the
low-to-high transition of the clock for predictable operation. Clock
triggering occurs at a voltage level and is not directly related to the
transition time of the positive-going pulse. Following the hold time
interval, data at the D input may be changed without affecting the
levels of the output.
LOGIC SYMBOL (IEEE/IEC)
4
3
2
1
10
11
12
13
5
6
9
8
&
S
S
C1
C2
R
1D
2D
R
SF00047
LOGIC DIAGRAM
VCC = Pin 14
GND = Pin 7
5, 9
6, 8
Q
Q
4, 10
1, 13
3, 11
2, 12
SD
RD
CP
D
SF00048
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
14-Pin Plastic DIP
–40
°C to +85°C
74ABT74 N
74ABT74 N
SOT27-1
14-Pin plastic SO
–40
°C to +85°C
74ABT74 D
74ABT74 D
SOT108-1
14-Pin Plastic SSOP Type II
–40
°C to +85°C
74ABT74 DB
74ABT74 DB
SOT337-1
14-Pin Plastic TSSOP Type I
–40
°C to +85°C
74ABT74 PW
74ABT74PW DH
SOT402-1


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