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GS832418B-200I 数据表(PDF) 6 Page - GSI Technology |
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GS832418B-200I 数据表(HTML) 6 Page - GSI Technology |
6 / 46 page Rev: 1.00 10/2001 6/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) D6 G I Output Enable; active low A7 ADV I Burst address counter advance enable; active low A5, A6 ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low P6 ZZ I Sleep Mode control; active high L6 FT I Flow Through or Pipeline mode; active low T6 LBO I Linear Burst Order mode; active low N6 SCD I Single Cycle Deselect/Dual Cycle Deselect Mode Control ( x72/x36 Versions) G6 MCH I Must Connect High A4 MCH I Must Connect High (x18 version) H6, J6, K6, M6 MCL Must Connect Low A8, N6 MCL Must Connect Low (x18 version) B6 BW I Byte Enable; active low F6 ZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) W3 TMS I Scan Test Mode Select W4 TDI I Scan Test Data In W8 TDO O Scan Test Data Out W9 TCK I Scan Test Clock E5, E6, E7, G5, G7, J5, J7, L5, L7, N5, N7, R5, R6, R7 VDD I Core power supply D3, D9, F3, F4, F5, F7, F8, F9, H3, H4, H5, H7, H8, H9, K5, K7, M3, M4, M5, M7, M8, M9, P3, P4, P5, P7, P8, P9, T3, T9 VSS I I/O and Core Ground E3, E4, E8, E9, G3, G4, G8, G9, J3, J4, J8, J9, L3, L4, L8, L9, N3, N4, N8, N9, R3, R4, R8, R9 VDDQ I Output driver power supply GS832418/36/72 209-Bump BGA Pin Description Pin Location Symbol Type Description |
类似零件编号 - GS832418B-200I |
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类似说明 - GS832418B-200I |
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