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GS815036AB-333I 数据表(PDF) 5 Page - GSI Technology |
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GS815036AB-333I 数据表(HTML) 5 Page - GSI Technology |
5 / 25 page GS815018/36AB-357/333/300/250 Product Preview Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.05 10/2005 5/25 © 2003, GSI Technology Write Operations Write operations are initiated when the write enable input signal (SW) and chip select (SS) are captured at logic 0 on a rising edge of the K clock (and falling edge of the K clock). Late Write In Late Write mode the RAM requires Data In one rising clock edge later than the edge used to load Address and Control. Late Write protocol has been employed on SRAMs designed for RISC processor L2 cache applications and in Flow Through mode NBT SRAMs. Byte Write Control The Byte Write Enable inputs (Bx) determine which bytes will be written. Any combination of Byte Write Enable control pins, including all or none, may be activated. A Write Cycle with no Byte Write inputs active is a write abort cycle. Byte write control inputs are captured by the same clock edge used to capture SW. Example of x36 Byte Write Truth Table Function SW Ba Bb Bc Bd Read H X X X X Write Byte A L L H H H Write Byte B L H L H H Write Byte C L H H L H Write Byte D L H H H L Write all Bytes L L L L L Write Abort L H H H H |
类似零件编号 - GS815036AB-333I |
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类似说明 - GS815036AB-333I |
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