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GS8342R08GE-200 数据表(PDF) 10 Page - GSI Technology |
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GS8342R08GE-200 数据表(HTML) 10 Page - GSI Technology |
10 / 37 page Preliminary GS8342R08/09/18/36E-333/300/250/200/167 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.02 8/2005 10/37 © 2003, GSI Technology FLXDrive-II Output Driver Impedance Control HSTL I/O SigmaCIO DDR-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is between 150 Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is implemented with discrete binary weighted impedance steps. Updates of pull-down drive impedance occur whenever a driver is producing a “1” or is High-Z. Pull-up drive impedance is updated when a driver is producing a “0” or is High-Z. Common I/O SigmaCIO DDR-II B4 SRAM Truth Table Kn LD R/W DQ Operation A + 0 A + 1 A + 2 A + 3 ↑ 1 X Hi-Z Hi-Z Hi-Z Hi-Z Deselect ↑ 0 0 D@Kn+1 D@Kn+1 D@Kn+2 D@Kn+2 Write ↑ 0 1 Q@Kn+1 or Cn+1 Q@Kn+2 or Cn+2 Q@Kn+2 or Cn+2 Q@Kn+3 or Cn+3 Read Note: Q is controlled by K clocks if C clocks are not used. |
类似零件编号 - GS8342R08GE-200 |
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类似说明 - GS8342R08GE-200 |
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