数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

GS8644Z36E-250V 数据表(PDF) 5 Page - GSI Technology

部件名 GS8644Z36E-250V
功能描述  72Mb Pipelined and Flow Through Synchronous NBT SRAM
Download  30 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  GSI [GSI Technology]
网页  http://www.gsitechnology.com
标志 GSI - GSI Technology

GS8644Z36E-250V 数据表(HTML) 5 Page - GSI Technology

  GS8644Z36E-250V Datasheet HTML 1Page - GSI Technology GS8644Z36E-250V Datasheet HTML 2Page - GSI Technology GS8644Z36E-250V Datasheet HTML 3Page - GSI Technology GS8644Z36E-250V Datasheet HTML 4Page - GSI Technology GS8644Z36E-250V Datasheet HTML 5Page - GSI Technology GS8644Z36E-250V Datasheet HTML 6Page - GSI Technology GS8644Z36E-250V Datasheet HTML 7Page - GSI Technology GS8644Z36E-250V Datasheet HTML 8Page - GSI Technology GS8644Z36E-250V Datasheet HTML 9Page - GSI Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 5 / 30 page
background image
Preliminary
GS8644Z18/36E-xxxV
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 6/2006
5/30
© 2003, GSI Technology
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable
inputs will deactivate the device.
Function
W
BA
BB
BC
BD
Read
H
X
X
X
X
Write Byte “a”
L
L
H
H
H
Write Byte “b”
L
H
L
H
H
Write Byte “c”
L
H
H
L
H
Write Byte “d”
L
H
H
H
L
Write all Bytes
L
L
L
L
L
Write Abort/NOP
L
H
H
H
H
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock.
The Byte Write Enable inputs (BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write
cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.


类似零件编号 - GS8644Z36E-250V

制造商部件名数据表功能描述
logo
List of Unclassifed Man...
GS8644Z36E-250 ETC-GS8644Z36E-250 Datasheet
1Mb / 39P
   72Mb Pipelined and Flow Through Synchronous NBT SRAM
logo
GSI Technology
GS8644Z36E-250 GSI-GS8644Z36E-250 Datasheet
556Kb / 32P
   72Mb Pipelined and Flow Through Synchronous NBT SRAM
logo
List of Unclassifed Man...
GS8644Z36E-250I ETC-GS8644Z36E-250I Datasheet
1Mb / 39P
   72Mb Pipelined and Flow Through Synchronous NBT SRAM
logo
GSI Technology
GS8644Z36E-250I GSI-GS8644Z36E-250I Datasheet
556Kb / 32P
   72Mb Pipelined and Flow Through Synchronous NBT SRAM
More results

类似说明 - GS8644Z36E-250V

制造商部件名数据表功能描述
logo
GSI Technology
GS8644Z36GE-200 GSI-GS8644Z36GE-200 Datasheet
556Kb / 32P
   72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8642Z18B GSI-GS8642Z18B Datasheet
1Mb / 34P
   72Mb Pipelined and Flow Through Synchronous NBT SRAM
logo
List of Unclassifed Man...
GS8644Z18 ETC-GS8644Z18 Datasheet
1Mb / 39P
   72Mb Pipelined and Flow Through Synchronous NBT SRAM
logo
GSI Technology
GS8642ZV18B GSI-GS8642ZV18B Datasheet
1Mb / 32P
   72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8640Z18T GSI-GS8640Z18T Datasheet
972Kb / 25P
   72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8640Z18T-V GSI-GS8640Z18T-V Datasheet
914Kb / 22P
   72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8644ZV18B GSI-GS8644ZV18B Datasheet
1Mb / 37P
   72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8640ZV18T GSI-GS8640ZV18T Datasheet
582Kb / 23P
   72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8640Z18GT-250I GSI-GS8640Z18GT-250I Datasheet
271Kb / 25P
   72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8322Z18 GSI-GS8322Z18 Datasheet
763Kb / 38P
   36Mb Pipelined and Flow Through Synchronous NBT SRAM
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30


数据表 下载

Go To PDF Page


链接网址




隐私政策
ALLDATASHEETCN.COM
ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com