Preliminary

GS8342D08/09/18/36E-333/300/250/200/167

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.02 8/2005

7/37

© 2003, GSI Technology

Background

Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are

needed. Therefore, the SigmaQuad-II SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O

SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from

Separate I/O SRAMs can cut the RAM’s bandwidth in half.

Alternating Read-Write Operations

SigmaQuad-II SRAMs follow a few simple rules of operation.

- Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port.

- Read or Write data transfers in progress may not be interrupted and re-started.

- R and W high always deselects the RAM.

- All address, data, and control inputs are sampled on clock edges.

In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for

details.

SigmaQuad-II B4 SRAM DDR Read

The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on

the Read Enable-bar pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command. Data

can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C are tied high), after the following

rising edge of K with a rising edge of C (or by K if C and C are tied high), after the next rising edge of K with a rising edge of C,

and after the following rising edge of K with a rising edge of C. Clocking in a high on the Read Enable-bar pin, R, begins a read

port deselect cycle.

SigmaQuad-II B4 Double Data Rate SRAM Read First

Read A

NOP

Read B

Write C

Read D

Write E

NOP

A

B

C

D

E

C

C+1

C+2

C+3

E

E+1

C

C+1

C+2

C+3

E

E+1

A

A+1

A+2

A+3

B

B+1

B+2

B+3

D

D+1

D+2

K

K

Address

R

W

BWx

D

C

C

Q

CQ

CQ