数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

GS8182Q18D-133I 数据表(PDF) 10 Page - GSI Technology

部件名 GS8182Q18D-133I
功能描述  18Mb Burst of 2 SigmaQuad-II SRAM
Download  28 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  GSI [GSI Technology]
网页  http://www.gsitechnology.com
标志 GSI - GSI Technology

GS8182Q18D-133I 数据表(HTML) 10 Page - GSI Technology

Back Button GS8182Q18D-133I Datasheet HTML 6Page - GSI Technology GS8182Q18D-133I Datasheet HTML 7Page - GSI Technology GS8182Q18D-133I Datasheet HTML 8Page - GSI Technology GS8182Q18D-133I Datasheet HTML 9Page - GSI Technology GS8182Q18D-133I Datasheet HTML 10Page - GSI Technology GS8182Q18D-133I Datasheet HTML 11Page - GSI Technology GS8182Q18D-133I Datasheet HTML 12Page - GSI Technology GS8182Q18D-133I Datasheet HTML 13Page - GSI Technology GS8182Q18D-133I Datasheet HTML 14Page - GSI Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 28 page
background image
Preliminary
GS8182Q18D-200/167/133
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 11/2004
10/28
© 2003, GSI Technology
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching
with a vendor-specified tolerance is between 150
Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as
the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for
drifts in supply voltage and temperature every 1024 cycles. A clock cycle counter periodically triggers an impedance evaluation,
resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the
optimum level. The output driver is implemented with discrete binary weighted impedance steps.
Burst of 2 Coherency and Pass Through Functions
Because the Burst of 2 read and write commands are loaded at the same time, there may be some confusion over what constitutes
“coherent” operation. Normally, one would expect a RAM to produce the just-written data when it is read immediately after a
write. This is true of the Burst of 2 except in one case, as is illustrated in the following diagram. If the user holds the same address
value in a given K clock cycle, loading the same address as a read address and then as a matching write address, the Burst of 2 will
read or “Pass-thru” the latest data input, rather than the data from the previously completed write operation.
Burst of 2 Coherency and Pass Through Functions
Dwg Rev. G
DB0
DB1
DD0
DD1
DF0
DF1
DH0
DH1
DI0
QA0
QA1
QC0
QC1
QE0
QE1
71
Write
Read
OO
IO
56
OI
3
Write
Read
Write
C
/R
/W
/BWx
Read
Write
Address
OO
OI
OI
OO
OO
OO
Read
K
/K
D
Q
??
5
/C
4
682
719
HI
ABCD
E
F
G
COHERENT
PASS-THRU


类似零件编号 - GS8182Q18D-133I

制造商部件名数据表功能描述
logo
GSI Technology
GS8182Q18BD-300M GSI-GS8182Q18BD-300M Datasheet
446Kb / 35P
   18Mb SigmaQuad-IITM Burst of 2 SRAM
More results

类似说明 - GS8182Q18D-133I

制造商部件名数据表功能描述
logo
GSI Technology
GS8182D19BD-375I GSI-GS8182D19BD-375I Datasheet
554Kb / 27P
   18Mb SigmaQuad-II Burst of 4 SRAM
GS8180QV18BD-167 GSI-GS8180QV18BD-167 Datasheet
414Kb / 28P
   18Mb Burst of 2 SigmaQuad SRAM
GS8180QV18BD-200 GSI-GS8180QV18BD-200 Datasheet
414Kb / 28P
   18Mb Burst of 2 SigmaQuad SRAM
GS8182D19BD-435I GSI-GS8182D19BD-435I Datasheet
554Kb / 27P
   18Mb SigmaQuad-II Burst of 4 SRAM
GS8180QV36BD-200I GSI-GS8180QV36BD-200I Datasheet
414Kb / 28P
   18Mb Burst of 2 SigmaQuad SRAM
GS8180QV18BD-200I GSI-GS8180QV18BD-200I Datasheet
414Kb / 28P
   18Mb Burst of 2 SigmaQuad SRAM
GS8180QV18BGD-167 GSI-GS8180QV18BGD-167 Datasheet
414Kb / 28P
   18Mb Burst of 2 SigmaQuad SRAM
GS8180QV18BGD-167I GSI-GS8180QV18BGD-167I Datasheet
414Kb / 28P
   18Mb Burst of 2 SigmaQuad SRAM
GS8182D37BD-435 GSI-GS8182D37BD-435 Datasheet
554Kb / 27P
   18Mb SigmaQuad-II Burst of 4 SRAM
GS8182D19BGD-333 GSI-GS8182D19BGD-333 Datasheet
554Kb / 27P
   18Mb SigmaQuad-II Burst of 4 SRAM
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28


数据表 下载

Go To PDF Page


链接网址




隐私政策
ALLDATASHEETCN.COM
ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com