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GS8171DW36AC-333I 数据表(PDF) 6 Page - GSI Technology |
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GS8171DW36AC-333I 数据表(HTML) 6 Page - GSI Technology |
6 / 33 page GS8171DW36/72AC-350/333/300/250 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.04 4/2005 6/33 © 2003, GSI Technology Double Late Write Double Late Write means that Data In is required on the third rising edge of clock. Double Late Write is used to implement Pipeline mode NBT SRAMs. Byte Write Control The Byte Write Enable inputs (Bx) determine which bytes will be written. Any combination of Byte Write Enable control pins, including all or none, may be activated. A Write Cycle with no Byte Write inputs active is a write abort cycle. Example of x36 Byte Write Truth Table Function W Ba Bb Bc Bd Read H X X X X Write Byte A L L H H H Write Byte B L H L H H Write Byte C L H H L H Write Byte D L H H H L Write all Bytes L L L L L Write Abort L H H H H SigmaRAM Double Late Write with Pipelined Read ADV DD Read Write Read Write Read CD F E CK Address A B /E1 /W DQ QA CQ Key QC Hi-Z Access DB |
类似零件编号 - GS8171DW36AC-333I |
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类似说明 - GS8171DW36AC-333I |
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