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GS8160E18BGT-250I 数据表(PDF) 7 Page - GSI Technology

部件名 GS8160E18BGT-250I
功能描述  1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
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制造商  GSI [GSI Technology]
网页  http://www.gsitechnology.com
标志 GSI - GSI Technology

GS8160E18BGT-250I 数据表(HTML) 7 Page - GSI Technology

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Mode Pin Functions
Mode Name
Pin Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H
Interleaved Burst
Output Register Control
FT
L
Flow Through
H or NC
Pipeline
Power Down Control
ZZ
L or NC
Active
H
Standby, IDD = ISB
GS8160E18/32/36BT-250/200/150
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 9/2005
7/23
© 2004, GSI Technology
Note:
Thereis a pull-up deviceonthe FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in
the default states as specified in the above tables.
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Burst Counter Sequences
BPR 1999.05.18
Byte Write Truth Table
Function
GW
BW
BA
BB
BC
BD
Notes
Read
H
H
X
X
X
X
1
Read
H
L
H
H
H
H
1
Write byte a
H
L
L
H
H
H
2, 3
Write byte b
H
L
H
L
H
H
2, 3
Write byte c
H
L
H
H
L
H
2, 3, 4
Write byte d
H
L
H
H
H
L
2, 3, 4
Write all bytes
H
L
L
L
L
L
2, 3, 4
Write all bytes
L
X
X
X
X
X
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.


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