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74ABTH16374BDGG 数据表(PDF) 6 Page - NXP Semiconductors |
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74ABTH16374BDGG 数据表(HTML) 6 Page - NXP Semiconductors |
6 / 10 page Philips Semiconductors Product specification 74ABT16374B 74ABTH16374B 16-bit D-type flip-flop; positive-edge trigger (3-State) 1998 Feb 27 6 AC CHARACTERISTICS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER WAVEFORM Tamb = +25°C VCC = +5.0V Tamb = –40 to +85°C VCC = +5.0V ±0.5V UNIT MIN TYP MAX MIN MAX fMAX Maximum clock frequency 1 180 260 MHz tPLH tPHL Propagation delay nCP to nQx 1 1.7 1.4 2.6 2.2 4.0 3.4 1.7 1.4 4.7 3.9 ns tPZH tPZL Output enable time to High and Low level 3 4 1.3 1.3 2.4 2.3 3.7 3.4 1.3 1.3 4.7 4.6 ns tPHZ tPLZ Output disable time from High and Low level 3 4 1.9 1.7 3.1 2.6 4.6 4.0 1.9 1.7 5.5 4.4 ns AC SETUP REQUIREMENTS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER WAVEFORM Tamb = +25°C VCC = +5.0V Tamb = –40 to +85°C VCC = +5.0V ±0.5V UNIT MIN TYP MIN ts(H) ts(L) Setup time, High or Low nDx to nCP 2 1.0 1.0 0.3 0.1 1.0 1.0 ns th(H) th(L) Hold time, High or Low nDx to nCP 2 1.0 1.0 –0.1 –0.3 1.0 1.0 ns tw(H) tw(L) nCP pulse width High or Low 1 2.8 2.8 1.2 1.5 2.8 2.8 ns AC WAVEFORMS VM = 1.5V, VIN = GND to 3.0V VM VM VM VM VM 1/fMAX tw(H) tw(L) tPHL tPLH nCP nQx SA00328 Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency VM nDx VM VM VM VM VM nCP ts(H) th(H) ts(L) th(L) NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SA00329 Waveform 2. Data Setup and Hold Times |
类似零件编号 - 74ABTH16374BDGG |
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类似说明 - 74ABTH16374BDGG |
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