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GS1531 数据表(PDF) 9 Page - Gennum Corporation |
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GS1531 数据表(HTML) 9 Page - Gennum Corporation |
9 / 49 page GS1531 Data Sheet 30573 - 4 July 2005 9 of 49 F10, F9, G10, G9, H10, H9, J10, J9, K10, K9 DIN[9:0] Synchronous with PCLK Input PARALLEL DATA BUS Signal levels are LVCMOS/LVTTL compatible. DIN9 is the MSB and DIN0 is the LSB. HD 20-bit mode SD/HD = LOW 20bit/10bit = HIGH Chroma data input in SMPTE mode SMPTE_BYPASS =HIGH DVB_ASI = LOW Data input in Data-Through mode SMPTE_BYPASS = LOW DVB_ASI = LOW HD 10-bit mode SD/HD = LOW 20bit/10bit = LOW High impedance in all modes. SD 20-bit mode SD/HD = HIGH 20bit/10bit = HIGH Chroma data input in SMPTE mode SMPTE_BYPASS = HIGH DVB_ASI = LOW Data input in Data-Through mode SMPTE_BYPASS = LOW DVB_ASI = LOW High impedance in DVB-ASI mode SMPTE_BYPASS = LOW DVB_ASI = HIGH SD 10-bit mode SD/HD = HIGH 20bit/10bit = LOW High impedance in all modes. G4 IOPROC_EN/DIS Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to enable or disable I/O processing features. When set HIGH, the following I/O processing features of the device are enabled: • EDH Packet Generation and Insertion (SD-only) • SMPTE 352M Packet Generation and Insertion • ANC Data Checksum Calculation and Insertion • Line-based CRC Generation and Insertion (HD-only) • Line Number Generation and Insertion (HD-only) • TRS Generation and Insertion • Illegal Code Remapping To enable a subset of these features, keep IOPROC_EN/DIS HIGH and disable the individual feature(s) in the IOPROC_DISABLE register accessible via the host interface. When set LOW, the I/O processing features of the device are disabled, regardless of whether the features are enabled in the IOPROC_DISABLE register. Table 1-1: Pin Descriptions (Continued) Pin Number Name Timing Type Description |
类似零件编号 - GS1531 |
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类似说明 - GS1531 |
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