N01L1618N1AB2-70I datasheet(5/10 Pages) NANOAMP

部件名	N01L1618N1AB2-70I

功能描述	1Mb Ultra-Low Power Asynchronous CMOS SRAM

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制造商	NANOAMP [NanoAmp Solutions, Inc.]

网页	http://www.nanoamp.com

标志

5 / 10 page

(DOC# 14-02-009 REV F ECN# 01-0995)

5

The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.

NanoAmp Solutions, Inc.

N01L1618N1A

Timing Test Conditions

Item

Input Pulse Level

0.1VCC to 0.9 VCC

Input Rise and Fall Time

5ns

Input and Output Timing Reference Levels

0.5 VCC

Output Load

CL = 30pF

Operating Temperature

-40 to +85 oC

Timing

Item

Symbol

1.65 - 2.2 V

1.8 - 2.2 V

Units

Min.

Max.

Min.

Max.

Read Cycle Time

tRC

85

70

ns

Address Access Time

tAA

85

70

ns

Chip Enable to Valid Output

tCO

85

70

ns

Output Enable to Valid Output

tOE

35

30

ns

Byte Select to Valid Output

tLB, tUB

30

25

ns

Chip Enable to Low-Z output

tLZ

10

ns

Output Enable to Low-Z Output

tOLZ

55

ns

Byte Select to Low-Z Output

tLBZ, tUBZ

10

ns

Chip Disable to High-Z Output

tHZ

30

25

ns

Output Disable to High-Z Output

tOHZ

30

25

ns

Byte Select Disable to High-Z Output

tLBHZ, tUBHZ

30

25

ns

Output Hold from Address Change

tOH

55

ns

Write Cycle Time

tWC

85

70

ns

Chip Enable to End of Write

tCW

50

40

ns

Address Valid to End of Write

tAW

50

40

ns

Byte Select to End of Write

tLBW, tUBW

50

40

ns

Write Pulse Width

tWP

50

40

ns

Address Setup Time

tAS

00

ns

Write Recovery Time

tWR

00

ns

Write to High-Z Output

tWHZ

25

20

ns

Data to Write Time Overlap

tDW

40

35

ns

Data Hold from Write Time

tDH

00

ns

End Write to Low-Z Output

tOW

10

ns

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