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Si5600
Preliminary Rev. 0.31
7
Table 3. AC Characteristics (RXDIN, RXDOUT, RXCLK1, RXCLK2)
(VDD = 1.8 V ±5%, TA = –40°C to 85°C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output Clock Frequency
(RXCLK1)
fclkout
—622
667
MHz
Duty Cycle (RXCLK1, RXCLK2)
tch/tcp, Figure 2
45
—
55
%
Output Rise and Fall Times
(RXCLK1, RXCLK2,RXDOUT)
tR,tF
Figure 3
—
50
—
ps
Data Invalid Prior to RXCLK1
tcq1
Figure 2
—
—
200
ps
Data Invalid After RXCLK1
tcq2
Figure 2
—
—
200
ps
Input Return Loss (RXIN)
400 kHz–10.0 GHz
10.0 GHz–16.0 GHz
18.7
TBD
—
—
—
—
dB
dB
Slicing Adjust Dynamic Range
SLICELVL = 200–800 mV
–20
—
20
mV
Slicing Level Offset1
(referred to RXDIN)
SLICELVL = 200–800 mV
–500
—
500
µV
Slicing Level Accuracy
VSLICE
–5
—
5
%
Sampling Phase Adjustment2
PHASEADJ = 200–800 mV
–45
°
—45o
LOS Threshold Dynamic Range
LOSLVL = 200–800 mV
10
—
50
mV
pk-pk
LOS Threshold Offset3
(referred to RXDIN)
LOSLVL = 200–800 mV
–500
—
500
µV
LOS Threshold Accuracy
VLOS
–5
—
5
%
Note:
1. Slice level (referred to RXDIN) is calculated as follows: VSLICE = (SLICE_LVL – 0.4 " VREF)/15.
2. Sample Phase Offset is calculated as follows: PHASE OFFSET = 45
° (PHASEADJ – 0.4 " VREF)/0.3
3. LOS Threshold voltage (referred to RXDIN) is calculated as follows: VLOS = 30 mV + (LOS_LVL – 0.4 " VREF)/15.
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