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DAC8831IDR 数据表(PDF) 5 Page - Burr-Brown (TI) |
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DAC8831IDR 数据表(HTML) 5 Page - Burr-Brown (TI) |
5 / 29 page www.ti.com PIN CONFIGURATION (NOT TO SCALE) 1 2 3 4 8 7 6 5 V DD DGND SDI SCLK V OUT AGND V REF CS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 RFB V OUT AGNDF AGNDS V REF−S V REF−F CS V DD INV DGND LDAC SDI NC SCLK DAC8831 Thermal Pad(1) 2 3 5 6 4 13 12 10 9 11 14 1 V DD RFB SCLK CS 8 7 NOTE: (1) Exposed thermal pad in the QFN package must be connected to analog ground. DAC8830 DAC8831 SLAS449C – FEBRUARY 2005 – REVISED NOVEMBER 2006 D PACKAGE D PACKAGE RGY PACKAGE SO-8 SO-14 QFN-14 (TOP VIEW) (TOP VIEW) (TOP VIEW) TERMINAL FUNCTIONS TERMINAL DESCRIPTION NO. NAME DAC8830 1 VOUT Analog output of DAC 2 AGND Analog ground 3 VREF Voltage reference input 4 CS Chip select input (active low). Data is not clocked into SDI unless CS is low 5 SCLK Serial clock input 6 SDI Serial data input. Data is latched into input register on the rising edge of SCLK. 7 DGND Digital ground 8 VDD Analog power supply, +3 V to +5 V DAC8831 1 RFB Feedback resistor. Connect to the output of external operational amplifier in bipolar mode. 2 VOUT Analog output of DAC 3 AGNDF Analog ground (Force) 4 AGNDS Analog ground (Sense) 5 VREF–S Voltage reference input (Sense). Connect to external voltage reference 6 VREF–F Voltage reference input (Force). Connect to external voltage reference 7 CS Chip select input (active low). Data is not clocked into SDI unless CS is low. 8 SCLK Serial clock input. 9 NC No internal connection 10 SDI Serial data input. Data is latched into input register on the rising edge of SCLK. Load DAC control input. Active low. When LDAC is Low, the DAC latch is simultaneously updated with the 11 LDAC content of the input register. 12 DGND Digital ground Junction point of internal scaling resistors. Connect to external operational amplifier inverting input in bipolar 13 INV mode. 14 VDD Analog power supply, +3 V to +5 V. 5 Submit Documentation Feedback |
类似零件编号 - DAC8831IDR |
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类似说明 - DAC8831IDR |
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