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TC51WHM516AXGN65 数据表(PDF) 4 Page - Toshiba Semiconductor |
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TC51WHM516AXGN65 数据表(HTML) 4 Page - Toshiba Semiconductor |
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4 / 11 page  TC51WHM516AXGN65,70 2002-03-14 4/11 AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta ==== −−−−25°C to 85°C, VDD ==== 2.6 to 3.3 V) (See Note 5 to 11) TC51WHM516AXGN 65 70 SYMBOL PARAMETER MIN MAX MIN MAX UNIT tRC Read Cycle Time 65 10000 70 10000 ns tACC Address Access Time 65 70 ns tCO Chip Enable ( CE1 ) Access Time 65 70 ns tOE Output Enable Access Time 25 25 ns tBA Data Byte Control Access Time 25 25 ns tCOE Chip Enable Low to Output Active 10 10 ns tOEE Output Enable Low to Output Active 0 0 ns tBE Data Byte Control Low to Output Active 0 0 ns tOD Chip Enable High to Output High-Z 20 20 ns tODO Output Enable High to Output High-Z 20 20 ns tBD Data Byte Control High to Output High-Z 20 20 ns tOH Output Data Hold Time 10 10 ns tPM Page Mode Time 65 10000 70 10000 ns tPC Page Mode Cycle Time 30 30 ns tAA Page Mode Address Access Time 30 30 ns tAOH Page Mode Output Data Hold Time 10 10 ns tWC Write Cycle Time 65 10000 70 10000 ns tWP Write Pulse Width 50 50 ns tCW Chip Enable to End of Write 60 60 ns tBW Data Byte Control to End of Write 60 60 ns tAS Address Set-up Time 0 0 ns tWR Write Recovery Time 0 0 ns tODW WE Low to Output High-Z 20 20 ns tOEW WE High to Output Active 0 0 ns tDS Data Set-up Time 30 30 ns tDH Data Hold Time 0 0 ns tCS CE2 Set-up Time 0 0 ns tCH CE2 Hold Time 300 300 µs tDPD CE2 Pulse Width 10 10 ms tCHC CE2 Hold from CE1 0 0 ns tCHP CE2 Hold from Power On 30 30 µs AC TEST CONDITIONS PARAMETER CONDITION Output load 30 pF + 1 TTL Gate Input pulse level VDD − 0.2 V, 0.2 V Timing measurements VDD × 0.5 Reference level VDD× 0.5 tR, tF 5 ns |
类似零件编号 - TC51WHM516AXGN65 |
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类似说明 - TC51WHM516AXGN65 |
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