数据搜索系统,热门电子元器件搜索 |
|
FAN6520BIM 数据表(PDF) 7 Page - Fairchild Semiconductor |
|
FAN6520BIM 数据表(HTML) 7 Page - Fairchild Semiconductor |
7 / 14 page 7 www.fairchildsemi.com FAN6520B Rev. 1.0.3 Figure 5. PC Board Small Signal Layout Guidelines Figure 5 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Minimize any leakage current paths on the COMP pin and locate the resistor, RPULLUP close to the COMP pin. Provide local VCC decoupling between VCC and GND pins. Locate the capacitor, CBOOT as close as practical to the BOOT and PHASE pins. All components used for feedback compen- sation should be located as close to the IC as practical. Feedback Compensation Figure 6 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the reference voltage level. The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the SW node. The PWM wave is smoothed by the output LC filter (LOUT and COUT). The modulator transfer function is the small-signal trans- fer function of VOUT/VCOMP. This function is dominated by a DC Gain and the output filter (LOUT and COUT), with a double pole break frequency at FLC and a zero at FESR. The DC Gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage ∆V OSC. The following equations define the modulator break fre- quencies as a function of the output LC filter: Figure 6. Voltage Mode Buck Converter Compensation Design 1. The compensation network consists of the error amplifier (internal to the FAN6520B) and the imped- ance networks ZIN and ZFB. The goal of the com- pensation network is to provide a closed loop transfer function with the highest 0dB crossing fre- quency (F0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at F0dB and 180 degrees. The equations below relate the compensation network’s poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 6. +VOUT Q2 VCC SW BOOT LOUT COUT GND CBOOT CVCC +5V DBOOT FAN6520B Q1 Vin F LC 1 2 π LC × ------------------------- = (15) F ESR 1 2 π ESR × C × ------------------------------------ = (16) Z FB COMP FB +VOUT Q2 L OUT COUT +5V VIN SW 0.8V ERROR AMP PWM OSC DETAILED COMPENSATION COMPONENTS COMP FB 0.8V ERROR AMP C1 R2 C3 R3 C2 R1 Z IN V OUT ZFB ZIN F Z1 1 2 πR 2C1 ---------------------- = (17) F P1 1 2 πR 2 C 1C2 C 1 C 2 + -------------------- ----------------------------------------- = (18) F Z2 1 2 πC 3 R1 R 3 + () ---------------------------------------- = (19) F P2 1 2 πR 3C3 ---------------------- = (20) |
类似零件编号 - FAN6520BIM |
|
类似说明 - FAN6520BIM |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |