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KM62V256CLTG-7L 数据表(PDF) 7 Page - Samsung semiconductor |
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KM62V256CLTG-7L 数据表(HTML) 7 Page - Samsung semiconductor |
7 / 12 page ELECTRONICS KM62V256C, KM62U256C Family CMOS SRAM Revision 04 April 1996 - 7 - TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE (1) (Address Controlled) (/CS=/OE=Vil, /WE=Vih) Address Data Out tRC Previous Data Valid Data Valid tAA tOH TIMING WAVEFORM OF READ CYCLE (/WE= VIH ) Notes (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ (max.) is less than tLZ(min.) both for a given device and from device to device. tRC tAA tCO tOE tOLZ(4) tOH tLZ tHZ tOHZ Address /CS /OE Data out Data Valid High - Z |
类似零件编号 - KM62V256CLTG-7L |
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类似说明 - KM62V256CLTG-7L |
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