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TC90A80N 数据表(PDF) 3 Page - Toshiba Semiconductor |
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TC90A80N 数据表(HTML) 3 Page - Toshiba Semiconductor |
3 / 23 page TC90A80N/F 2002-12-04 3 Pin Functions Pin No. Pin Name Function DC Level (V) Interface Circuit 1 BIAS ADC bias pin Connect a 0.01-µF capacitor between this pin and pin 5 (VSS1). 1.3 2 VRT ADC bias pin Sets upper limit of range D for ADC. Connect a 0.01-µF capacitor between this pin and pin 5 (VSS1). The output voltage is held at internal level. 3.16 3 VDD1 ADC power supply pin (analog) Apply the same voltage as that of pin 23 (VDD2). 5.0 Internally connected to pin 23 (VDD2). 4 CIN Chrominance signal input pin (I 2C Bus function: NR) Because the signal is internally center-biased, it should be applied after cutting the DC component using a capacitor of around 0.01 µF. 2.5 5 VSS1 ADC GND pin (analog) Set the same voltage as that of pin 26 (VSS2). 0.0 Internally connected to pin 26 (VDD2). 6 VRB ADC bias pin Sets lower limit of range D for ADC. Connect a 0.01-µF capacitor between this pin and pin 5 (VSS1). The output voltage is held at internal level. 1.83 7 YIN Luminance signal input pin (I 2C Bus function: NR) Because sync tip clamp is internally used, the signal should be applied after cutting the DC component using a capacitor of around 0.47 µF. Sync Tip NR Mode : 1.86 YCS Mode : 1.83 8 TEST Pin for reset control and test control when shipping. Reset control: Applying pulse of 10 µs or longer while the pin is at High with power on resets all the I 2C bus settings to 0. For normal use, set the pin to Low. 0.0 1 2 20 Ω 4 20 Ω 15 kΩ 7 20 Ω 20 Ω 6 20 Ω 8 150 Ω |
类似零件编号 - TC90A80N |
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类似说明 - TC90A80N |
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