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74LVX163MTC 数据表(PDF) 2 Page - National Semiconductor (TI) |
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74LVX163MTC 数据表(HTML) 2 Page - National Semiconductor (TI) |
2 / 8 page Functional Description The LVX163 counts in modulo-16 binary sequence From state 15 (HHHH) it increments to state 0 (LLLL) The clock inputs of all flip-flops are driven in parallel through a clock buffer Thus all changes of the Q outputs occur as a result of and synchronous with the LOW-to-HIGH transition of the CP input signal The circuits have four fundamental modes of operation in order of precedence synchronous reset parallel load count-up and hold Four control inputs Synchronous Reset (MR) Parallel Enable (PE) Count En- able Parallel (CEP) and Count Enable Trickle (CET)deter- mine the mode of operation as shown in the Mode Select Table A LOW signal on MR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP With PE and MR HIGH CEP and CET permit counting when both are HIGH Conversely a LOW signal on either CEP or CET inhibits counting The LVX163 uses D-type edge-triggered flip-flops and changing the MR PE CEP and CET inputs when the CP is in either state does not cause errors provided that the rec- ommended setup and hold times with respect to the rising edge of CP are observed The Terminal Count (TC) output is HIGH when CET is HIGH and counter is in state 15 To implement synchronous multi- stage counters the TC outputs can be used with the CEP and CET inputs in two different ways Figure 1 shows the connections for simple ripple carry in which the clock period must be longer than the CP to TC delay of the first stage plus the cumulative CET to TC de- lays of the intermediate stages plus the CET to CP setup time of the last stage This total delay plus setup time sets the upper limit on clock frequency For faster clock rates the carry lookahead connections shown in Figure 2 are rec- ommended In this scheme the ripple delay through the in- termediate stages commences with the same clock that causes the first stage to tick over from max to min in the Up mode or min to max in the Down mode to start its final cycle Since this final cycle takes 16 clocks to complete there is plenty of time for the ripple to progress through the intermediate stages The critical timing that limits the clock period is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchro- nous reset for flip-flops registers or counters When the Output Enable (OE) is LOW the parallel data outputs O0– O3 are active and follow the flip-flop Q outputs A HIGH signal on OE forces O0–O3 to the High Z state but does not prevent counting loading or resetting Logic Equations Count Enable e CEP CET PE TC e Q0 Q1 Q2 Q3 CET Mode Select Table MR PE CET CEP Action on the Rising Clock Edge ( L ) L X X X Reset (Clear) H L X X Load (Pn x Qn) H H H H Count (Increment) H H L X No Change (Hold) H H X L No Change (Hold) H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial State Diagram TLF12157 – 4 TLF12157 – 5 FIGURE 1 TLF12157 – 6 FIGURE 2 http www nationalcom 2 |
类似零件编号 - 74LVX163MTC |
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类似说明 - 74LVX163MTC |
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