SN74GTLPH1655 datasheet(9/16 Pages) TI

部件名	SN74GTLPH1655

功能描述	16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER

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制造商	TI [Texas Instruments]

网页	http://www.ti.com

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Live-Insertion Specifications for B Port

Timing Requirements

SN74GTLPH1655

16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE

UNIVERSAL BUS TRANSCEIVER

SCES294C – OCTOBER 1999 – REVISED MAY 2005

over operating free-air temperature range

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Ioff

VCC = 0,

BIAS VCC = 0,

VI or VO = 0 to 1.5 V

10

µA

IOZPU

VCC = 0 to 1.5 V,

BIAS VCC = 0,

VO = 0.5 V to 1.5 V, OE = 0

±30

µA

IOZPD

VCC = 1.5 V to 0,

BIAS VCC = 0,

VO = 0.5 V to 1.5 V, OE = 0

±30

µA

VCC = 0 to 3.15 V

5

mA

ICC (BIAS VCC)

BIAS VCC = 3.15 V to 3.45 V,

VO (B port) = 0 to 1.5 V

VCC = 3.15 V to 3.45 V

10

µA

VO

VCC = 0,

BIAS VCC = 3.3 V

IO = 0

0.95

1.05

V

IO

VCC = 0,

BIAS VCC = 3.15 V to 3.45 V,

VO (B port) = 0.6 V

–1

µA

over recommended ranges of supply voltage and operating free-air temperature,

V

TT = 1.5 V and VREF = 1 V for GTLP (unless otherwise noted)

MIN

MAX

UNIT

fclock

Clock frequency

175

MHz

LEAB or LEBA high

3

tw

Pulse duration

ns

CLK high or low

3

A before CLK

3

B before CLK

3

tsu

Setup time

ns

A before LEAB

↓, CLK = don't care

2.5

B before LEBA

↓, CLK = don't care

2.5

A after CLK

0.5

B after CLK

0.5

th

Hold time

ns

A after LEAB

↓, CLK = don't care

0.5

B after LEBA

↓, CLK = don't care

0.5

9

类似零件编号 - SN74GTLPH1655

制造商	部件名	数据表	功能描述
Texas Instruments	SN74GTLPH1612	157Kb / 15P	[Old version datasheet] 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER
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	SN74GTLPH1616DGGR	351Kb / 18P	[Old version datasheet] 17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS
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类似说明 - SN74GTLPH1655

制造商	部件名	数据表	功能描述
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