HCPL-576X datasheet(7/11 Pages) HP

部件名	HCPL-576X

功能描述	AC/DC to Logic Interface Hermetically Sealed Optocouplers

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制造商	HP [Agilent(Hewlett-Packard)]

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7

Parameter

Symbol

Typ.

Units

Conditions

Fig.

Note

I

HYS

1.2

mA

I

HYS = ITH+ - ITH-

Hysteresis

1

V

HYS

1.1

V

HYS = VTH+ - VTH-

Input Clamp Voltage

V

ILC

-0.76

V

ILC = V2 - V3; V3 = GND;

I

IN = -10 mA

Bridge Diode

V

D1,2

0.62

I

IN = 3 mA (see schematic)

Forward Voltage

V

D3,4

0.73

Input-Output Resistance

R

I-O

1012

Ω

V

I-O = 500 Vdc

9

Input-Output Capacitance

C

I-O

2.0

pF

f = 1 MHz, V

I-O = 0 Vdc

Input Capacitance

C

IN

50

pF

f = 1 MHz; V

IN = 0 V,

Pins 2 & 3, Pins 1 & 4 Open

Output Rise Time

t

r

10

µs7

(10-90%)

Output Fall Time

t

f

0.5

µs7

(90-10%)

Typical Characteristics All typical values are at T

A

= 25

°C, V

CC

= 5 V, unless otherwise specified.

Notes:

1. Maximum operating frequency is

defined when output waveform (Pin 6)

attains only 90% of VCC with RL = 1.8

k

Ω, CL = 15 pF using a 5 V square

wave input signal.

2. Measured at a point 1.6 mm below

seating plane.

3. Current into/out of any single lead.

4. Surge input current duration is 3 ms at

120 Hz pulse repetition rate. Transient

input current duration is 10

µs at

120 Hz pulse repetition rate. Note that

maximum input power, PIN, must be

observed.

5. Derate linearly above 100

°C free-air

temperature at a rate of 4.26 mW/

°C.

Maximum input power dissipation of

195 mW allows an input IC junction

temperature of 150

°C at an ambient

temperature of TA = 125°C with a

typical thermal resistance from

junction to ambient of

θJAi = 235°C/W.

The typical thermal resistance from

junction to case is equal to 170

°C/W.

Excessive PIN and TJ may result in

device degradation.

6. The 1.8 k

Ω load represents 1 TTL unit

load of 1.6 mA and the 4.7 k

Ω pull-up

resistor.

7. Logic low output level at Pin 6 occurs

under the conditions of VIN ≥ VTH+ as

well as the range of VIN > VTH – once

VIN has exceeded VTH+. Logic high

output level at Pin 6 occurs under the

conditions of VIN ≤ VTH- as well as the

range of VIN < VTH+ once VIN has

decreased below VTH-.

8. The ac voltage is instantaneous

voltage.

9. Device considered a two terminal

device: Pins 1, 2, 3, 4 connected

together, Pins 5, 6, 7 8 connected

together.

10. This is a momentary withstand test,

not an operating condition.

11. The tPHL propagation delay is

measured from the 2.5 V level of the

leading edge of a 5.0 V input pulse (1

µs rise time) to the 1.5 V level on the

leading edge of the output pulse (see

Figure 7).

12. The tPLH propagation delay is

measured from the 2.5 V level of the

trailing edge of a 5.0 V input pulse (1

µs fall time) to the 1.5 V level on the

trailing edge of the output pulse (see

Figure 7).

13. Common mode transient immunity in

Logic High level is the maximum

tolerable dVCM/dt of the common mode

voltage, VCM, to ensure that the output

will remain in a Logic High state (i.e.,

VO > 2.0 V). Common mode transient

immunity in Logic Low level is the

maximum tolerable dVCM/dt of the

common mode voltage, VCM, to ensure

that the output will remain in a Logic

Low state (i.e., VO < 0.8 V). See

Figure 8.

14. In applications where dVCM/dt may

exceed 50,000 V/

µs (such as static

discharge), a series resistor, RCC,

should be included to protect the

detector IC from destructively high

surge currents. The recommended

value for RCC is 240 Ω per volt of

allowable drop in VCC (between Pin 8

and VCC) with a minimum value of

240

Ω.

15. D1 and D2 are Schottky diodes; D3

and D4 are zener diodes.

16. Standard parts receive 100% testing at

25

°C (Subgroups 1 and 9). SMD,

Class H and Class K parts receive

100% testing at 25, 125, and -55

°C

(Subgroups 1 and 9, 2 and 10 ,3 and

11, respectively.)

17. Parameters shall be tested as part of

device initial characterization and after

process changes. Parameters shall be

guaranteed to the limits specified for

all lots not specifically tested.

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