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KM6161002BI 数据表(PDF) 8 Page - Samsung semiconductor |
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KM6161002BI 数据表(HTML) 8 Page - Samsung semiconductor |
8 / 9 page KM6161002B, KM6161002BI CMOS SRAM Rev 2.0 - 8 - February 1998 FUNCTIONAL DESCRIPTION * NOTE : X means Don ′t Care. CS WE OE LB UB Mode I/O Pin Supply Current I/O1~I/O8 I/O9~I/O16 H X X* X X Not Select High-Z High-Z ISB, ISB1 L H H X X Output Disable High-Z High-Z ICC L X X H H L H L L H Read DOUT High-Z ICC H L High-Z DOUT L L DOUT DOUT L L X L H Write DIN High-Z ICC H L High-Z DIN L L DIN DIN NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS, WE, LB and UB. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10.When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. Address CS Valid Data UB, LB WE Data in Data out TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LB Controlled) tWC tCW(3) tBW tWP(2) tDH tDW tWR(5) tAW tAS(4) High-Z High-Z(8) tBLZ tWHZ(6) High-Z |
类似零件编号 - KM6161002BI |
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类似说明 - KM6161002BI |
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