M74DW66500B70ZT datasheet(6/19 Pages) STMICROELECTRONICS

部件名	M74DW66500B70ZT

功能描述	2x 64Mbit (x8/ x16, Multiple Bank, Boot Block) Flash Memory and 32Mbit Pseudo SRAM, 3V Supply, Multiple Memory Product

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制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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6 / 19 page

M74DW66500B

6/19

SIGNAL DESCRIPTION

See Figure 2 Logic Diagram and Table 1,Signal

Names, for a brief overview of the signals connect-

ed to this device.

Address Inputs (A0-A21). Address lines A0-A20

are common inputs for the Flash Memory and

PSRAM components. Address line A21 is an input

that is common for the two Flash Memory compo-

nents. The Address Inputs select the cells in the

memory array to access during Bus Read opera-

tions. During Bus Write operations they control the

commands sent to the Command Interface of the

internal state machine. The Flash memory is ac-

cessed through the Chip Enable (EF) and Write

Enable (W) signals, while the PSRAM is accessed

through two Chip Enable signals (E1S and E2S)

and the Write Enable signal (W).

Data Inputs/Outputs (DQ0-DQ7). The Data I/O

outputs the data stored at the selected address

during a Bus Read operation. During Bus Write

operations they represent the commands sent to

the Command Interface of the Program/Erase

Controller.

Data Inputs/Outputs (DQ8-DQ14). The Data I/O

outputs the data stored at the selected address

during a Bus Read operation when BYTE is High,

VIH. When BYTE is Low, VIL, these pins are not

used and are high impedance. During Bus Write

operations the Command Register does not use

these bits. When reading the Status Register

these bits should be ignored.

Data Input/Output or Address Input (DQ15A–

1). When BYTE is High, VIH, this pin behaves as

a Data Input/Output pin (as DQ8-DQ14). When

BYTE is Low, VIL, this pin behaves as an address

pin; DQ15A–1 Low will select the LSB of the ad-

dressed Word, DQ15A–1 High will select the MSB.

Throughout the text consider references to the

Data Input/Output to include this pin when BYTE is

High and references to the Address Inputs to in-

clude this pin when BYTE is Low except when

stated explicitly otherwise.

Flash-1 Chip Enable (EF1) and Flash-2 Chip En-

able (EF2). The Chip Enable input activates the

memory to which it is attached, allowing Bus Read

and Bus Write operations to be performed. When

Chip Enable is High, VIH, all other pins are ig-

nored.

Output Enable (G). The Output Enable, G, con-

trols the Bus Read operation of the Flash Memory

and PSRAM components.

Write Enable (W). The Write Enable, W, controls

the Bus Write operation of the Flash Memory and

PSRAM components.

VPP/Write Protect (VPP/WP). The

VPP/Write

Protect pin provides two functions. The VPP func-

tion allows the Flash memory to use an external

high voltage power supply to reduce the time re-

quired for Program operations. This is achieved

by bypassing the unlock cycles and/or using the

multiple Word (2 or 4 at-a-time) or multiple Byte

Program (2, 4 or 8 at-a-time) commands. The

Write Protect function provides a hardware meth-

od of protecting the four outermost boot blocks

(two at the top, and two at the bottom of the ad-

dress space).

When VPP/Write Protect is Low, VIL, the memory

protects the four outermost boot blocks; Program

and Erase operations in these blocks are ignored

while VPP/Write Protect is Low, even when RPF is

at VID.

When VPP/Write Protect is High, VIH, the memory

reverts to the previous protection status of the four

outermost boot blocks (two at the top, and two at

the bottom of the address space). Program and

Erase operations can now modify the data in these

blocks unless the blocks are protected using Block

Protection.

When VPP/Write Protect is raised to VPP the mem-

ory automatically enters the Unlock Bypass mode.

When VPP/Write Protect returns to VIH or VIL nor-

mal operation resumes. During Unlock Bypass

Program operations the memory draws IPP from

the pin to supply the programming circuits. See the

description of the Unlock Bypass command in the

Command Interface section. The transitions from

VIH to VPP and from VPP to VIH must be slower

than tVHVPP. See the M29DW640D datasheet for

more details.

Never raise VPP/Write Protect to VPP from any

mode except Read mode, otherwise the memory

may be left in an indeterminate state.

The VPP/Write Protect pin must not be left floating

or unconnected or the device may become unreli-

able. A 0.1µF capacitor should be connected be-

tween the VPP/Write Protect pin and the VSS

Ground pin to decouple the current surges from

the power supply. The PCB track widths must be

sufficient to carry the currents required during

Unlock Bypass Program, IPP.

Reset/Block Temporary Unprotect (RPF). The

Reset/Block Temporary Unprotect pin can be

used to apply a Hardware Reset to the memory or

to temporarily unprotect all Blocks that have been

protected.

Note that if VPP/WP is at VIL, then the two outer-

most boot blocks will remain protected even if RPF

is at VID.

A Hardware Reset is achieved by holding Reset/

Block Temporary Unprotect Low, VIL, for at least

tPLPX. After Reset/Block Temporary Unprotect

goes High, VIH, the memory will be ready for Bus

Read and Bus Write operations after tPHEL or

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