1st Level X Side Data Path Select Function Table

Inputs

Data Path

Control

Mode

Function

SA2X(1)

SA2X(0)

MODE

SC

CP

IN

From

To

RegPort

Internal Node

L

L

L

X

A B C D

(A B C D) X

ASYNC

Transparent datapath from Port (A

B C D) to internal node (A B C

D) X

L

H

L

X

(A B C D) IR

(A B C D) X

ASYNC

Clocked Path Contents of Input

Register (A B C D) IR to internal

node (A B C D) X

H

L

L

X

(A B C D) OR

(A B C D) X

ASYNC

Readback contents of Output

register (A B C D) OR to internal

node (A B C D) X

H

H

L

X

GND

(A B C D) X

ASYNC

Diagnostic Select all 36 bits as low

and pass to the internal node (A

B C D) X

(Notes 2 3)

(Notes 2 3)

H (Note 1)

L

(Note 3)

(Note 3)

SYNC

(Note 3)

Note 1

Low to High transitions of MODE

SC must be immediately preceeded by a low to high transition (clock edge) on CP

IN while holding Synchronous

Control Inputs SA2X(0) and SA2X(1) steady to preset internal sync registers and assure predictable operation during the control mode change from asynchronous

to synchronous

Note 2

SA2X(0) and SA2X(1) levels are synchronously asserted by the positive transition of CP

IN when MODE

SC is high

Note 3

IN

2nd Level X Side Data Path Select Function Table for Port X

Inputs

Data Path

Control

Mode

Function

XSEL(1)

XSEL(0)

MODE

SC

CP

IN

From

To

Internal Node

Port

L

L

L

X

AX

X

ASYNC

Internal Node AX to Port X

L

H

L

X

BX

X

ASYNC

Internal Node BX to Port X

H

L

L

X

CX

X

ASYNC

Internal Node CX to Port X

H

H

L

X

DX

X

ASYNC

Internal Node DX to Port X

(Notes 2 3)

(Notes 2 3)

H (Note 1)

L

(Note 3)

(Note 3)

SYNC

(Note 3)

Note 1

Low to High transitions of MODE

SC must be immediately preceeded by a low to high transition (clock edge) on CP

IN while holding Synchronous

Control Inputs XSEL(0) and XSEL(1) steady to preset internal sync registers and assure predictable operation during the control mode change from asynchronous

to synchronous

Note 2

XSEL(0) and XSEL(1) levels are synchronously asserted by the positive transition of CP

IN when MODE

SC is high

Note 3

IN

2nd Level X Side Data Path Select Function Table for Port Y

Inputs

Data Path

Control

Mode

Function

YSEL

MODE

SC

CP

IN

From

To

Internal Node

Port

L

L

X

BX

Y

ASYNC

Internal Node BX to Port Y

H

L

X

DX

Y

ASYNC

Internal Node DX to Port Y

(Notes 2 3)

H (Note 1)

L

(Note 3)

(Note 3)

SYNC

(Note 3)

Note 1

Low to High transitions of MODE

SC must be immediately preceeded by a low to high transition (clock edge) on CP

IN while holding Synchronous

Control Inputs YSEL steady to preset internal registers and assure predictable operation during the control mode change from asynchronous to synchronous

Note 2

YSEL levels are synchronously asserted by the positive transition of CP

IN when MODE

SC is high

Note 3

IN

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